Jingling Xue

Energy-aware compilers are becoming increasingly important for embedded systems due to the need to meet a variety of design constraints on time, code size and power consumption. This paper introduces for the first time a trace-based, link-time compiler framework on binaries for embedded systems and evaluates its potential benefits in supporting energy optimisations, especially those that exploit the interaction between compilers and architecture. We present two algorithms for reducing leakage energy in functional units and data caches, respectively. Both algorithms work uniformly at the granularity of optimisation regions that are formed by the hot traces of a program. Our experimental results using Mediabench benchmarks show that good leakage energy savings can be achieved at the cost of some small performance and code size penalties. Furthermore, by varying the granularity of optimisation regions, which is a tunable parameter, embedded application programmers can make the tradeoffs between energy savings and these associated costs. © 2006 Elsevier B.V. All rights reserved.

Data tiling is an array layout transformation technique that partitions an array into smaller subarray blocks. It was originally proposed to improve the cache performance of regular loops. Recently, researchers have applied this technique to scratchpad memory (SPM) allocation. Arrays whose sizes exceed a given SPM size can be tiled or divided into smaller subarray blocks or tiles and the program performance can be significantly improved by placing the smaller subarray tiles in SPM. Existing data tiling techniques are applicable to regularly-accessed arrays in individual loop nests. In embedded applications, arrays are often accessed in multiple loop nests via possibly aliased pointers. Tiling arrays in a loop nest alone will often affect the tiling and allocation decisions for arrays accessed in other loop nests. Moreover, tiling arrays accessed via aliased pointers is difficult since their access patterns are unknown at compile time. This paper presents a new data tiling approach to address these practical issues. We perform alias profiling to detect the most likely memory access patterns and use an ILP solver to select the best tiling schemes for all loop nests in the program as a whole. We have integrated data tiling in an existing SPM allocation framework. Our preliminary experimental results show that our approach can improve significantly the performance of a set of programs selected from the Mediabench suite. © Springer-Verlag Berlin Heidelberg 2007.

We introduce a new approach to computing interprocedural modification side effects for part of an object-oriented program (e.g., components, libraries or client modules). Our approach consists of first performing a whole-program points-to analysis to such an incomplete program and then applying a so-called mutability analysis (MA) to determine which objects in the program are mutable by unknown code and which references and call sites in the program are complete (since their points-to sets and target methods are statically resolvable). Based on these results, we present a new MA-based interprocedural side-effect analysis for computing the modification side-effects for an incomplete program. Our experimental results show that our mutability analysis enables a variety of pure methods to be detected, yielding the purity information useful in program understanding and debugging. In addition, our MA-based side-effect analysis enables more redundant loads to be removed than a recent TBAA-based PRE algorithm guided by type-based alias analysis (TBAA). Our approach is simple since it is flow-insensitive and achieves these improvements at small costs. © 2006 Elsevier Inc. All rights reserved.