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Jingling Xue's Information Page

Jingling Xue

Professor & Associate HoS

Research Areas
To update this page please go to myCSE.
Office:	K17 501L
Phone:	+61 2 9385 4889 (Internal: x54889)
Fax:	+61 2 9385 5995 (Internal: x55995)
Email:
Mail:	School of Computer Science and Engineering The University of New South Wales Sydney 2052, Australia
	Compiler Optimisations Computer Architecture Object-Oriented Languages Compilers for Embedded Systems Parallelising and Optimising Compilers Parallel and Distributed Computing
Publications
	Validity Invariants And Effects Y Lu, J Potter, J Xue, ECOOP 2007---Object oriented programming, E. Ernst. Springer, Berlin, 2007, pp. 202 - 227
	Trace-Based Leakage Energy Optimisations At Link Time L Li, J Xue, Journal of Systems Architecture, . , 2007, pp. 1 - 20
	Towards Data Tiling For Whole Programs In Scratchpad Memory Allocation H Wu, H Feng, J Xue, L Li, Advances in compiler system architecture, L. Choi. Springer Verlag, Heidelberg, D-69121, Germany, Heidelberg, D-69121, Germany, 2007, pp. 63 - 74
	Toward Automatic Data Distribution For Migrating Computations L Pan, J Xue, M Lai, M Dillencourt, L Bic, 2007 International conference on parallel processing, Proceedings, . IEEE computer society, USA, 2007, p. 27
	Scratchpad Allocation For Data Aggregates In Superperfect Graphs L Li, Q Nguyen, J Xue, 2007 ACM conference on languages, compilers and tools for embedded systems, Proceedings, S. Pande and Z. Li. ACM press, New York, USA, 2007, pp. 207 - 216
	Loop Recreation For Thread-Level Speculation G Lin, L Li, J Xue, T Ngai, 2007 international conference on parallel and distributed systems, Proceedings, C. King. IEEE computer society, 2007, pp. 1 - 10
	Interprocedural Side-Effect Analysis For Incomplete Object-Oriented Software Modules J Xue, P Nguyen, J Potter, Journal of Systems Software, . Elsevier, The Netherlands, 2007, pp. 92 - 105
	Data Cache Locking For Tight Timing Calculations X Vera, B Lisper, J Xue, ACM transactions on embedded computing systems, . ACM, New York, USA, 2007, pp. 1 - 38
	Trace-Based Cache Leakage Reduction At Link Time J Xue, L Li, Advances in computer systems architecture, 11th Asia-Pacific conference, Proceeidngs, C. Jesshope, C. Egan. Springer, Germany, 2006, pp. 175 - 189
	Partial Dead Code Elimination On Predicated Code Regions J Xue, Q Cai, G Lin, Software -- Practice and Engineering, R.N. Horspool & A.J. Wellings. John Wiley & Sons, Inc., USA, 2006, pp. 1655 - 1685
	Minimizing Bank Selection Instructions For Partitioned Memory Architectures B Scholz, B Burgstaller, J Xue, Proceedings of the 2006 International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, Krisztian Flautner and Taewhan Kim. ACM Press, New York, USA, 2006, pp. 201 - 211
	Instruction Scheduling With Release Times And Deadlines On Ilp Processors H Wu, J Jaffar, J Xue, 12th IEEE international conference on embedded and real-time computing systems, Proceedings, S. Petters, S. Hong. IEEE, Los Alamitos, CA, USA, 2006, pp. 51 - 60
	Coopstream: A Cooperative Cache Based Streaming Schedule Scheme For On-Demand Media Services On Overlay Networks B Bao, M Guo, J Xue, International conference on parallel processing, Proceedings, W. Feng. IEEE computer society, USA, 2006, pp. 577 - 584
	Code Tiling: One Size Fits All J Xue, Q Huang, High-performance computing: paradigm and infrastructure, L. Yang, M. Guo. Wiley, USA, 2006
	A Lifetime Optimal Algorithm For Speculative Pre J Xue, Q Cai, ACM Transactions on Architecture and Code Optimization, Brad Calder and Dean Tullsen. ACM Press, New York, USA, 2006, pp. 115 - 155
	A Fresh Look At Pre As A Maximum Flow Problem J Xue, J Knoop, International conference on compiler construction, A. Mycroft, A. Zeller. Springer Verlag, Germany, 2006, pp. 139 - 154
	Special Section On Advanced Computer Systems Architecture - Forward P Yew, J Xue, Journal of Computer Science and Technology, . Science Press, Beijing, 2005
	Memory Coloring: A Compiler Approach For Scratchpad Memory Management L Li, J Xue, G Lin, Proceedings of the 14th International conference on parallel architectures and compilation, . IEEE computer society, Los alamitos, CA, USA, 2005, pp. 329 - 338
	Interprocedural Side-Effect Analysis And Optimisation In The Presence Of Dynamic Class Loading P Nguyen, J Xue, Computer science 2005: 28th australasian computer science conference, . Australian computer society inc, Flinders university, 2005, pp. 9 - 18
	Improving The Performance Of Gcc By Exploiting Ia-64 Architectural Features X Yang, J Xue, C Yang, Advances in Computer systems architecture, 10 Asia-Pacific conference, . Springer-Verlag Berlin, Berlin, 2005, pp. 236 - 251
	Enabling Loop Fusion And Tiling For Cache Performance By Fixing Fusion-Preventing Data Dependencies J Xue, Q Huang, M Guo, Proceedings of the 2005 international conference on parallel processing, . IEEE computer society, Los Alamitos, CA, USA, 2005, pp. 107 - 115
	Completeness Analysis For Incomplete Object-Oriented Programs J Xue, P Nguyen, Compiler construction, . Springer-Verlag Berlin, Berlin, Germany, 2005, pp. 271 - 286
	Aggressive Loop Fusion For Improving Locality And Parallelism J Xue, Parallel and distributed processing and applications, . Springer-Verlag Berlin, Berlin, 2005, pp. 224 - 238
	Region-Based Partial Dead Code Elimination On Predicated Code Q Cai, L Gao, J Xue, Compiler Construction: 13th International Conference, E. Duesterwald. Springer, Germany, 2004, pp. 150 - 166
	Interprocedural Side-Effect Analysis And Optimisation In The Presence Of Dynamic Class Loading P Nguyen, J Xue, Proceedings of the 28th Australasian Computer Science Conference (ACS2005), Vladimir Estivill-Castro. Australian Computer Society Inc., Australia, 2004, pp. 9 - 18
	Efficient And Accurate Analytical Modeling Of Whole-Program Data Cache Behaviour J Xue, X Vera, IEEE Transactions on Computers, Virtor K. Prasanna. IEEE, USA, 2004, pp. 547 - 566
	A Trace-Based Binary Compilation Framework For Energy-Aware Computing J Xue, L Li, Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Language, Compilers, and Tools for Embedded Systems (LCTES'04), R. Cytron. ACM, USA, 2004, pp. 95 - 106
	A Comparative Study Of Web Application Design Models Using The Java Technologies B Kurniawan, J Xue, Advanced Web Technologies and Applications, Jeffery Yu, et al. Springer Verlag, Germany, 2004, pp. 711 - 721
	Optimal And Efficient Speculation-Based Partial Redundancy Elimination Q Cai, J Xue, Int. Symposium on Code Generation and Optimization (CGO'03), W. Wwu. IEEE Computer Society, USA, 2003, pp. 91 - 102
	Data Caches In Mutitasking Hard Real-Time Systems X Vera, B Lisper, J Xue, 24th IEEE International Real-Time Systems Symposium, R. Rajkumar. IEEE Computer Society, USA, 2003, pp. 154 - 165
	Data Cache Locking For Higher Program Predictability X Vera, B Lisper, J Xue, Proc of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, J. Rexford, W. Sanders. ACM, USA, 2003, pp. 272 - 282
	Code Tiling For Improving The Cache Performance Of Pde Solvers Q Huang, J Xue, X Vera, 2003 International Conference on Parallel Processing, P. Sadayyappan and ChSing Yang. IEEE Computer Society, USA, 2003, pp. 615 - 624
	Time-Minimal Tiling When Rise Is Larger Than Zero J Xue, W Cai, Parallel Computing, . Elsevier Sciences B.V., North-Holland, 2002, pp. 915 - 936
	Space-Time Equations For Non-Unimodular Mappings J Xue, P Lenders, International Journal of Computer Mathematics, . Taylor and Francis Group, London, 2002, pp. 552 - 572
	Let's Study Whole-Program Cache Behaviour Analytically J Xue, X Vera, Proceedings of Eighth International Symposium on High-Performane Computer Architecture, David J. Lilja; Pen-Chung Yew. IEEE Computer Society, USA, 2002, pp. 176 - 185
	Eigenvectors-Based Parallelisation Of Nested Loops With Affine Dependences J Xue, P Lenders, Parallel Algorithms and Applications, . Taylor & Francis, UK, 2002, pp. 237 - 248
	Efficient Compile-Time Analysis Of Cache Behaviour For Programs With If Statements J Xue, X Vera, 2002 5th International Conference on Algorthms and Archiectures for Parallel Processing, Wanlei Zhou; Xue-Bin Chi; Andrzej Goscinsku; Guo-Jie Li. IEEE Computer Society, USA, 2002, pp. 396 - 407
	On Nonsingular Loop Transformations Using Suif's Dependence Abstraction J Xue, The 2nd international conference on parallel and distributed computing, applications and technologies, Yen-Chun Lin and Hong Shen. Tamkang University, TAIWAN, 2001, pp. 331 - 336
	Time-Minimal And Processor-Time-Minimal Loop Tiling J Xue, 2000 4th International Confernece on Algorithms and Architectures for Parallel Processing, . World Scientific, Singapore, 2000, pp. 264 - 280
	Researching The Modern Army" The Royal Australian Corps Of Transport E Greenhalgh, P Tang, J Xue, Army Journal, . Army Journal, Packapunyal, 2000, pp. 95 - 100
	Optimal Tiling For Loops With Parallelogram Iteration Spaces S Chen, J Xue, Proceedings of 1st International Conference on Parallel and Distributed Applications and Technologies, . University of Hongkong, Hongkong, 2000, pp. 117 - 124
	Loop Tiling For Parallelism J Xue, , . Kluwer Academic Publishers, Boston, 2000
	Partitioning And Scheduling Loops On Nows S Chen, J Xue, International Journal of Computer Communications, . Elsevier, The Netherlands, 1999, pp. 1017 - 1033
	Communication Overhead On Distributed Memory Machines S Chen, J Xue, The 4th Australian Computer Architecture Conference, . Springer-Verlag, Singapore, 1999, pp. 227 - 238

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