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Sri Parameswaran's Information Page

Sri Parameswaran

Professor & Program Director - Computer Engineering

Research Areas
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Office:	K17 510D
Phone:	+61 2 9385 7223 (Internal: x57223)
Fax:	+61 2 9385 5995 (Internal: x55995)
Email:
Mail:	School of Computer Science and Engineering The University of New South Wales Sydney 2052, Australia
	Hardware Software Co-Design VLSI Systems Low Power Design
Publications
	CUFFS: An Instruction Count based Architectural Framework for Security of MPSoCs (None HERDC) R Ragel, S Parameswaran, K Patel, Proceedings of the Design, Automation and Test in Europe (DATE'09) Conference, . IEEE Press, 2009, 779-784
	Rijid: Random Code Injection To Mask Power Analysis Based Side Channel Attacks J Ambrose, R Ragel, S Parameswaran, 2007 Design automation conference, Proceedings, L. Stok and S. Sapatnekar. ACM, Piscataway, NJ, USA, 2007, pp. 489 - 492
	Instruction Trace Compression For Rapid Instruction Cache Simulation A Janapsatya, A Ignjatovic, S Parameswaran, J Henkel, DATE 07, Kathy Preas. Institute of Electrical and Electronics Engineers Inc., Piscataway, NJ 08855-1331, United States, 2007, pp. 803 - 808
	Ensuring Secure Program Execution In Multiprocessor Embedded Systems: A Case Study K Patel, S Parameswaran, S Shee, CODES + ISSS 2007, N. Dutt, and J. Teich. ACM, New York, USA, 2007, pp. 57 - 62
	Energy Driven Application Self-Adaptation At Run-Time J Peddersen, S Parameswaran, 20th international conference on VLSI design/6th international conference on Embedded systems, Proceedings, L. O'Conner. IEEE, Los Alamitos, CA, USA, 2007, pp. 385 - 390
	Design Methodology For Pipelined Heterogeneous Multiprocessor System S Shee, S Parameswaran, 44th Design automation conference, Proceedings, . ACM press, New York, USA, 2007, pp. 811 - 816
	Clipper: Counter-Based Low Impact Processor Power Estimation At Run-Time J Peddersen, S Parameswaran, Proceedings of the ASP-DAC 2006, L. O'Conner. IEEE, Piscataway, NJ, USA, 2007, pp. 890 - 895
	Automatic Application Specific Floating-Point Unit Generation Y Chong, S Parameswaran, Design, automation and test in Europe 2007, Proceedings, K. Preas. EDAA, Leuven, 2007, pp. 461 - 466
	Automatic Application Speciﬁc Floating-point Unit Generation (None HERDC) Y Chong, Y Chong, S Parameswaran, Design, Automation and Test in Europe, K. Preas.. EDAA, 2007, 461-466
	A Smart Random Code Injection To Mask Power Analysis Based Side Channel Attacks S Parameswaran, R Ragel, J Ambrose, CODES + ISSS 2007, N. Dutt, and J. Teich. ACM, New York, USA, 2007, pp. 51 - 56
	A Power-Efficient 5.6-Ghz Process-Compensated Cmos Frequency Divider I Lu, N Weste, S Parameswaran, IEEE Transactions on Circuits and Systems II-Express Briefs, . IEEE, Los Amitos, CA, USA, 2007, pp. 323 - 327
	Minimising The Energy Consumption Of Real-Time Tasks With Precedence Constraints On A Single Processor H Wu, S Parameswaran, Embedded and ubiquitous computing 2006, Proceedings, E. Sha, et al.. Springer, Germany, 2006, pp. 45 - 56
	Impres: Integrated Monitoring For Processor Reliability And Security S Parameswaran, R Ragel, 43rd Design automation conference 2006, Proceedings, . ACM press, New York, 2006, pp. 502 - 505
	Heterogenous Multiprocessor Implementations For Jpeg: A Case Study S Shee, A Erdos, S Parameswaran, Proceedings of the International Conference on Hardware/Software Code design and System Synthesis CODES+ISSS 2006, S Ha, K.Choi. ACM Press, New York, USA, 2006, pp. 217 - 222
	Hardware Assisted Pre-emptive Cont. Fl. Chking. for Emb. Processors to improve Reliability (None HERDC) R Ragel, S Parameswaran, Proceedings of the 4th International CODES, . ACM Press, New York, 2006, 100-105
	Finding Optimal L1 Cache Configuration For Embedded Systems A Janapsatya, A Ignjatovic, S Parameswaran, ASPDAC 2006, Proceedings, H. Onodera, Y. Matsunaga. IEEE, USA, 2006, pp. 796 - 801
	Exploiting Statistical Information For Implementation Of Instruction Scratchpad Memory In Embedded Systems A Janapsatya, A Ignjatovic, S Parameswaran, IEEE transactions on VLSI systems, P. Eles, A. Jantsch. IEEE, USA, 2006, pp. 816 - 829
	Customization Of Application Specific Heterogeneous Multi-Pipeline Processors S Radhakrishnan, H Guo, S Parameswaran, Design, automation and test in europe, Proceedings, K. Preas. ACM press, New York, 2006, pp. 746 - 751
	Adc Precision Requirement For Digital Ultra-Wideband Receivers With Sublinear Front-Ends: A Power And Performance Perspective I Lu, N Weste, S Parameswaran, 19th Conference on VLSI Design, . Institute of Electrical and Electronics Engineers Computer Society, Piscataway, NJ 08855-1331, Unite, 2006, pp. 575 - 580
	A Novel Instruction Scratchpad Memory Optimization Method Based On Concomitance Metric A Janapsatya, A Ignjatovic, S Parameswaran, ASPDAC 2006, Proceedings, H. Onodera, Y. Matsunaga. IEEE, USA, 2006, pp. 612 - 617
	The Effect Of Receiver Front-End Non-Linearity On Ds-Uwb Systems Operating In The 3 To 4ghz Band I Lu, N Weste, S Parameswaran, Proceedings of IEEE international wireless networking conference, . IEEE, Piscataway, NJ, USA, 2005, pp. 776 - 781
	Rapid Embedded Hardware/Software System Generation J Peddersen, S Shee, A Janapsatya, S Parameswaran, Proceedings of VLSI Design 2005, . IEEE Computer society, Los Alamitos, CA, USA, 2005, pp. 111 - 116
	Novel Architecture For Loop Acceleration: A Case Study S Shee, S Parameswaran, N Cheung, Proceedings of the 3rd IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, . ACM press, New York, USA, 2005, pp. 297 - 302
	Nocee: Energy Macro-Model Extraction Methodology For Network On Chip Routers J Chan, S Parameswaran, Proceedings of the 2005 international conference on computer aided design, . IEEE, Piscataway, USA, 2005, pp. 254 - 259
	Micro Monitoring For Security In Application Specific Instruction-Set Processors R Ragel, S Parameswaran, S Kia, CASES 2005, . ACM press, New York, USA, 2005, pp. 304 - 314
	Instruction Code Mapping For Performance Increase And Energy Reduction In Embedded Computer Systems S Parameswaran, J Henkel, IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, . Ieee-Inst Electrical Electronics Engineers Inc, Piscataway, Nj, USA, 2005, pp. 498 - 502
	Balancing System Level Pipelines With Stage Voltage Scaling H Guo, S Parameswaran, Proceedings of IEEE annual symposium on VLSI, . IEEE Computer society, CA, USA, 2005, pp. 287 - 289
	Remcode: Relocating Embedded Code For Improving System Efficiency A Janapsatya, J Henkel, S Parameswaran, IEE Proceedings Computer Digital Technology, Professor Petru Eles. IEE, Oxford, UK, 2004, pp. 457 - 465
	Nocgen: A Template Based Reuse Methodology For Networks On Chip Architecture J Chan, S Parameswaran, Proceedings. 17th International Conference on VLSI Design 2004, Deeber Azada. IEEE, Piscataway,NJ, 2004, pp. 717 - 720
	Mince: Matching Instructions With Combinational Equivalence For Extensible Processor N Cheung, S Parameswaran, J Henkel, J Chan, Proceedings of DATE (volume II), G. Gielen and J. Figueras. IEEE Computer Society, New York, 2004, pp. 1020 - 1025
	Hardware/Software Managed Scratchpad Memory For Embedded Systems A Janapsatya, S Parameswaran, A Ignjatovic, Proceedings of ICCAD2004, . IEEE, New Jersey, USA, 2004, pp. 370 - 377
	Dual-Pipeline Heterogeneous Asip Design S Parameswaran, H Guo, S Radhakrishnan, Intlernational Conference on Hardware/Software Codesign and System Synthesis, . ACM, USA, 2004, pp. 12 - 17
	A Quantitative Study And Estimation Models For Extensible Instructions In Embedded Processors N Cheung, S Parameswaran, J Henkel, ICCAD-2004 IEEE/ACM Digest of Technical Papers, IEEE Computer Society. IEEE Computer Society, New York, 2004, pp. 183 - 189
	Rapid Configuration & Instruction Selection For An Asip:A Case Study N Cheung, J Henkel, S Parameswaran, Embedded Software for, A. Jerraya, S. Yoo, D. Verkest,N. Wehn. Kluwer Academic Publishers, Boston, USA, 2003
	Inside: Instruction Selection/Identification & Design Exploration For Extensible Processors N Cheung, S Parameswaran, J Henkel, IEEE/ACM Digestof Technical Papers (ICCAD-2003), Hidetoshi Onodera. The Association of Computing Machinery, New York, USA, 2003, pp. 291 - 297
	A Digital Ultra-Wideband Multiband Transceiver Architecture With Fast Frequency Hopping Capabilities I Lu, N Weste, S Parameswaran, 2003 IEEE Conference on Ultra Wideband Systems and Technologies Conference Proceedings, Jeffrey H.Reed. IEEE, Piscataway, NJ, USA, 2003, pp. 448 - 452
	Swasad: An Asic Design For High Speed Dna Sequence Matching S Parameswaran, Proceedings-of-ASP-DAC/VLSI-Design-2002.-7th-Asia-and-South-Pacific-Design-Automation-Conference-and-15h-International-Conference-on-VLSI-Design. 2002, Sunil D. Sherlekar. IEEE Comput. Soc, Los Alamitos, CA, USA, California, USA, 2002, pp. 541 - 546

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