Thesis Topic Details

Topic ID:
1200
Title:
Scheduling Instructions on Clustered VLIW processors
Supervisor:
Hui Wu
Research Area:
Compiler, Algorithms
Associated Staff
Assessor:
Jingling Xue
Topic Details
Status:
Active
Type:
R & D
Programs:
CS CE BIOM BINF SE
Group Suitable:
No
Industrial:
No
Pre-requisites:
Strong in algorithms and compilers.
Description:
Compared to a single register file in a traditional VLIW processor, a clustered VLIW processor has a register file in each cluster. If data is transferred from one cluster to another, a communication delay exists. In this project, you will work out efficient techniques for scheduling instructions in a basic block and design an instruction scheduler for a clustered VLIW processor. The optimization objective of your instruction scheduler is minimizing the total execution time of all instructions in a basic block.
Comments:
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