Drowsy and Decay Leakage Control for the Register File/Cache Memory Architecture
Supervisor:
Annie Guo
Research Area:
Embedded Systems, Computer architecuture, Low power systems
Associated Staff
Assessor:
Sri Parameswaran
Topic Details
Status:
Active
Type:
R & D
Programs:
CE
Group Suitable:
No
Industrial:
No
Pre-requisites:
COM3211, COMP3222
Description:
Leakage power is becoming the dominant portion of the chip power for 100ns CMOS technology and below. To reduce the leakage power, the drowsy or decay approach can be adopted. This project is to investigate how the approach can be effectively used in a hierarchical memory system to reduce its leakage power consumption.
