Thesis Topic Details
Topic ID: |
3222 | |
Title: |
Modelling of I/O devices for automatic device-driver synthesis | |
Supervisor: |
Leonid Ryzhyk | |
Research Area: |
Operating Systems | |
| Associated Staff | ||
|---|---|---|
Assessor: |
Peter Chubb | |
| Topic Details | ||
Status: |
Active | |
Type: |
Research | |
Programs: |
CS CE SE | |
Group Suitable: |
No | |
Industrial: |
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Pre-requisites: |
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Description: |
Device-driver development is a notoriously difficult and error-prone task. An alternative approach to manually writing device drivers is to automatically synthesize them from a formal specification of the device and a specification of the interface between the driver and the OS. In this project you will develop specifications of several I/O devices for use in driver synthesis. Such a specification constitutes a model of device operation written in a high-level hardware description language (HDL) such as SystemVerilog or DML. You will then use these specifications to synthesise working drivers for the selected devices. In the course of this work you will identify limitations in the synthesis tool and will work with other students and researchers on improving the tool and the underlying algorithms. |
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Comments: |
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| Past Student Reports | ||
| No Reports Available. Contact the supervisor for more information.
Check out all available reports in the CSE Thesis Report Library. NOTE: only current CSE students can login to view and select reports to download. |
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