Thesis Topic Details
Topic ID: |
3233 | |
Title: |
Automated Code Partitioning for MPSoC Architectures | |
Supervisor: |
Jude Angelo Ambrose | |
Research Area: |
Compiler, Computer architecuture, Embedded Systems | |
| Associated Staff | ||
|---|---|---|
Assessor: |
Jorgen Peddersen | |
| Topic Details | ||
Status: |
Active | |
Type: |
R & D | |
Programs: |
CE | |
Group Suitable: |
No | |
Industrial: |
No | |
Pre-requisites: |
COMP3131 | |
Description: |
Multiprocessor System-on-Chip (MPSoC) is a major component in state-of-the-art embedded systems, such as mobile phones, PDAs, Pads, etc. There exist different architectures such as pipeline, cluster, co-processor, grid, etc. A sequential code or a code written to a specific architecture requires extensive modification to be transferred to another architecture. Hence an automatic code partitioning for a given architecture will significantly reduce the time and effort for the designer in code partitioning. The expected outcome of this project is a software tool which partitions the code to a specific MPSoC architecture. As the first part, the student will be converting the sequential code to a generic model, such as Kahn Process Networks (KPN). The KPN compliant code will then be merged and modified to be mapped in a specific architecture. |
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Comments: |
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| Past Student Reports | ||
| No Reports Available. Contact the supervisor for more information.
Check out all available reports in the CSE Thesis Report Library. NOTE: only current CSE students can login to view and select reports to download. |
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