Thesis Topic Details

Topic ID:
3234
Title:
FPGA implementation of ASIP Processors
Supervisor:
Jude Angelo Ambrose
Research Area:
Computer architecuture, Embedded Systems
Associated Staff
Assessor:
Jorgen Peddersen
Topic Details
Status:
Active
Type:
R & D
Programs:
CE SE
Group Suitable:
Yes
Industrial:
No
Pre-requisites:
VHDL programming skills, COMP2121
Description:
The goal of this project is to implement an Application Specific Instruction Set processor in FPGA.

This project is highly practical and will provide an in-depth knowledge in processor design.
Comments:
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Past Student Reports
  Amanda WATTERS in s2, 2012
FPGA implementation of ASIP Processors
  Jinshui ZHU in s2, 2012
FPGA implementation of ASIP Processors
 

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