Thesis Topic Details
Topic ID: |
3272 | |
Title: |
Design of Synthetic Aperture Radar (SAR) Application Specific Instruction Set Processor (ASIP) | |
Supervisor: |
Ediz Cetin | |
Research Area: |
Computer architecuture, Embedded Systems | |
| Associated Staff | ||
|---|---|---|
Assessor: |
Andrew Dempster | |
| Topic Details | ||
Status: |
Active | |
Type: |
R & D | |
Programs: |
CS CE | |
Group Suitable: |
Yes | |
Industrial: |
No | |
Pre-requisites: |
-- | |
Description: |
This project aims to propose an Application Specific Instruction Set Processor (ASIP)architecture to implement Synthetic Aperture Radar (SAR) processing targeted to FPGA devices. Project will investigate and propose an instruction-set dedicated for SAR applications along with the design and realisation of suitable control and data-path architectures. This project will be co-supervised with Dr Robert Middleton at the Australian Centre for Space Engineering Research (ACSER) Skills required: Good VHDL and Computer Architecture Skills |
|
Comments: |
-- | |
| Past Student Reports | ||
| James LAUGHLIN in s2, 2012 Design of Synthetic Aperture Radar (SAR) Application Specific Instruction Set Processor (ASIP) |
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