Thesis Topic Details
Topic ID: |
3273 | |
Title: |
Configurable Low-power FFT Processor Design and Implementation for Synthetic Aperture Radar (SAR) Applications | |
Supervisor: |
Ediz Cetin | |
Research Area: |
Embedded Systems, Configurable system | |
| Associated Staff | ||
|---|---|---|
Assessor: |
Andrew Dempster | |
| Topic Details | ||
Status: |
Active | |
Type: |
R & D | |
Programs: |
CS CE | |
Group Suitable: |
No | |
Industrial: |
No | |
Pre-requisites: |
-- | |
Description: |
This project is concerned with the design, verification and FPGA implementation of a configurable FFT processor design for SAR application. VHDL model of the configurable FFT processor will be undertaken, along with logic-level simulations for verification and synthesis of the design targeting Xilinx FPGAs. Skills required: VHDL, Xilinx ISE and Implementation Skills |
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Comments: |
-- | |
| Past Student Reports | ||
| No Reports Available. Contact the supervisor for more information.
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