Thesis Topic Details
Topic ID: |
3340 | |
Title: |
VPR assessment of a novel circuit partitioning methodology | |
Supervisor: |
Oliver Diessel | |
Research Area: |
Reconfigurable computing, Algorithms, CAD for FPGAs | |
| Associated Staff | ||
|---|---|---|
Assessor: |
Sri Parameswaran | |
| Topic Details | ||
Status: |
Active | |
Type: |
R & D | |
Programs: |
CS CE BIOM BINF SE | |
Group Suitable: |
Yes | |
Industrial: |
No | |
Pre-requisites: |
Algorithms background; good coding skills; comp arch background desirable but not essential | |
Description: |
This project involves developing, implementing and assessing algorithms for partitioning digital circuits that are to be implemented on FPGA devices. The goal is to assess a novel circuit partitioning methodology we have developed for detecting and mitigating radiation-induced faults in space-based FPGA systems. Algorithms for partitioning, placing and routing circuits using open source frameworks are to be developed. The performance of the algorithms relative to a vanilla implementation of the framework is to be assessed. Requisite skills are the ability to work with a large, open source code base; the ability to understand the objectives of the project, for which some background in digital circuits would be useful; and the desire to work on a real research project. The project is suited to software engineering, computer science, computer or electrical engineering students. | |
Comments: |
Our aim is to write a research paper on the results. | |
| Past Student Reports | ||
| No Reports Available. Contact the supervisor for more information.
Check out all available reports in the CSE Thesis Report Library. NOTE: only current CSE students can login to view and select reports to download. |
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