Thesis Topic Details

Topic ID:
3358
Title:
Adaptive Pipelined Processing on Tilera
Supervisor:
Haris Javaid
Research Area:
Embedded Systems, Parallel Systems
Associated Staff
Assessor:
Sri Parameswaran
Topic Details
Status:
Active
Type:
R & D
Programs:
CS CE
Group Suitable:
No
Industrial:
No
Pre-requisites:
--
Description:
The emergence of multicore processors has presented a new challenge for parallel programming. Software pipelining technique exploits the parallelism in a given system by overlapping the execution of multiple steps within a loop. These independent steps can be mapped onto different processors and communicate in a pipelined fashion. Software pipelining is widely used for multimedia application like video encoding/decoding etc.
Traditionally, individual stages of pipeline are assigned to processors at design time, just considering the worst-case performance requirement. However, analysis shows that this technique is not energy efficient because most of the time system is not operating in worst-case scenario. In this project we will study the implementation of adaptive pipelined system where number of processors assigned to each stage depends on dynamic workload requirements. In this way extra processors can be switched off using power gating or clock gating technique. This work will be an extension to our previous work that proved the concept using software simulations. For this project, actual framework will be implemented using TileraPro64 chip which has 64 full processors on a chip. Students involved in this project will get hands on experience for programming future massively parallel multicore architectures.
Comments:
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Past Student Reports
 
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