Thesis Topic Details

Topic ID:
3359
Title:
An ASIP Generation Tool
Supervisor:
Haris Javaid
Research Area:
Computer architecuture
Associated Staff
Assessor:
Sri Parameswaran
Topic Details
Status:
Active
Type:
R & D
Programs:
CE
Group Suitable:
No
Industrial:
No
Pre-requisites:
--
Description:
A tool to generate Application Specific Instruction set Processors (ASIPs) by drag-dropping components. The output should be VHDL/Verilog. Components should include standard pipeline stages, data hazard unit, data forward unit, etc.
Comments:
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