The CORG group is conducting research in programming language implementations, compiler optimisations, computer architecture and compiler support for embedded systems. Our research has been supported by a number of competitive national research and industry grants.

The group has weekly meetings during which we discuss research topics in the areas of programming languages and compilers. Often, the topics are related to our current research projects consisting of student presentations regarding their recent progress. From time to time, there will be seminars centred around discussing one or more papers related to a given topic, with a "discussion leader" presenting the papers and answering the questions.

If you would like to be added to the group's mailing list or are interested in giving a talk, please send an email to me.

Staff

• Professor Jingling Xue
  

PhD Students

• Lin Gao
• Peng Di
• Anderson Kuei-An Ku
• Jenny Yi-Chun Kuo
• Lei Shang
• Qing Wan
• Xinwei Xie
• Xuemeng Zhang

Research Associate

• Yi Lu
  

Visiting PhD Student

• Lin Gao, Lian Li, Jingling Xue and Tin-Fook Ngai. Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction. In 2009 International Conference on Compiler Construction (CC'09), pages 78 -- 93, York, UK, 2009. (PDF)

• Lin Gao, Quan Hoang Nyugen, Lian Li, Jingling Xue and Tin-Fook Ngai. Thread-Sensitive Modulo Scheduling for Multicore Processors. In 2008 International Conference on Parallel Processing (ICPP'08), pages 132 -- 140, Portland, Oregon, 2008. (PDF)

• L. Gao, L. Li, J. Xue and T.K  Ngai. Loop Recreation for Thread-Level Speculation. In 2007 International Conference on Parallel and Distributed Systems (ICPADS'07), Hsingchu, Taiwan, 2007. (PDF)

  Backend Optimisations

  1. J. Xue and Q. Cai. A lifetime optimal algorithm for speculative PRE. ACM Transaction on Architecture and Code Generation, 3(2):115-155, 2006. (PDF)

  2. J. Xue and J. Knoop. A fresh look at PRE as a maximum flow problem. In 2006 International Conference on Compiler Construction (CC'06), pages 139 -- 154, Vienna, Austria, 2006. (PDF)

  3. J. Xue, Q. Cai and L. Gao. Partial dead code elimination on predicated code regions. Software -- Practice and Engineering, 36(15): 1655-1685, 2006.

  4. C. Yang, X. Yang and J. Xue. Improving the Performance of GCC by Exploiting IA-64 Architectural Features. In 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC'05) , pages 236 -- 251, Singapore, 2005. (Postscript)

  5. Q. Cai and L. Gao and J. Xue. Region-based partial dead code elimination on predicated code. In 2004 International Conference on Compiler Construction (CC'04) , pages 150 -- 166, Barcelona, Spain, 2004. (Postscript)

  6. Q. Cai and J. Xue. Optimal and efficient speculation-based partial redundancy elimination. In 1st Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'03) , pages 91 -- 102, San Francisco, 2003. (Postscript)

  Cache Analyses and Optimisations

  1. X. Vera, B. Lisper and J. Xue. Data Cache Locking for Tight Timing Calculations. ACM Transactions on Embedded Systems (TECS), 7(1):?--?, 2007.

  2. J.  Xue, Q. Huang and M. Guo. Enabling Loop Fusion and Tiling for Cache Performance by Fixing Fusion-Preventing Data Dependences. In 2005 International Conference on Parallel Processing (ICPP'05), pages 107 - 115, Oslo, Norway, 2005. (Postscript)

  3. J. Xue and Q. Huang. Code Tiling: One Size Fits All. In G. T. Yang and M. Guo, editors, High Performance Computing: Paradigm and Infrastructure , Chapter 11, pages 219--240. John Wiley & Sons Inc., 2004.

  4. J. Xue and X. Vera. Efficient and accurate analytical modeling of whole-program data cache behavior. IEEE Transactions on Computers, 53(5):547--566, 2004.

  5. X. Vera, B. Lisper and J. Xue. Data caches in multitasking hard real-time systems. In 24th IEEE International Real-Time Systems Symposium (RTSS'03), pages 154 -- 165, Cancun, Mexico, 2003. (Postscript)

  6. Q. Huang, J. Xue and X. Vera. Code tiling for improving the cache performance of PDE solvers. In 2003 International Conference on Parallel Processing (ICPP'03), pages 615 -- 626, Kaohsiung, Taiwan, 2003. (Postscript)

  7. X. Vera, B. Lisper and J. Xue. Data cache locking for higher program predictability. In 2003 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'03) , pages 272 - 282, San Diego, 2003. (Postscript)

  8. X. Vera and J. Xue. Let's study whole-program cache behaviour analytically. In 8th International Symposium on High-Performance Computer Architecture (HPCA-8), pages 175 -- 186, Boston, MA, 2002 (Postscript)

  9. X. Vera and J. Xue. Efficient compile-time analysis of cache behavior for programs with IF statements. In 5th International Conference on Algorithms and Architectures for Parallel Processing (ICA³PP'02) , pages 396-407, Beijing, 2002.

  10. J. Xue and C.-H. Huang. Reuse-driven tiling for improving data locality. International Journal of Parallel Programming, 26(6):671-696, 1998. (Postscript)

  Compiler Techniques for Embedded Systems

  1. Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li and Guibin Wang. Exploiting Loop-Dependent Stream Reuse for Stream Processors. In 17th International Conference on Parallel Architectures and Compilation Techniques (PACT'08) , pages 28 -- 37, Toronto, 2008. (PDF)

  2. Xuejun Yang, Li Wang, Jingling Xue, Yu Deng and Ying Zhang. Comparability Graph Coloring for Optimizing Utilization of Stream Register Files in Stream Processors. In 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'09) , pages 111 -- 120, North Carolina, 2009. (PDF)

  3. L. Wang, X. Yang, J. Xue, Y. Deng, X. Yan, T. Tang and Q. H. Nguyen. Optimizing Scientific Application Loops on Stream Processors. In ACM SIGPLAN/SIGBED 2008 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), pages 161 -- 170, Tucson, AZ, 2008.

  4. L. Li, H. Wu, H. Feng and J. Xue. Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. In 12th Asia-Pacific Computer Systems Architecture Conference (ACSAC'07), pages 63 -- 74, Seoul, Korea, 2007.

  5. B. Scholz, B. Burgstaller and J. Xue. Minimizing Bank Selection Instructions for Partitioned Memory Architectures. ACM Transactions on Embedded Computing Systems (TECS) , 7(2), 2008.

  6. L. Li, Q. H. Nguyen and J. Xue. Scratchpad Allocation for Data Aggregates in Superperfect Graphs. In ACM SIGPLAN/SIGBED 2007 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), pages 207 -- 216, San Diego, 2007. (PDF)

  7. L. Li and J. Xue. Trace-based Leakage Energy Optimisations at Link Time. Journal of Systems Architecture, 53(1):1--20, 2007.

  8. B. Scholz, B. Burgstaller and J. Xue. Minimizing Bank Selection Instructions for Partitioned Memory Architectures} In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'06), pages 201--211, Seoul, Korea, 2006. (One of the Four Best Paper Candidates) (PDF)

  9. H. Wu, J. Jaffar and J. Xue. Instruction Scheduling with Release Times and Deadlines on ILP Processors In 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), pages 51--60, Sydney, Australia, 2006. (PDF)

  10. L. Li and J. Xue. Trace-based Data Cache Leakage Reduction at Link Time. In 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC'06), pages 175--188, Shanghai, China, 2006.

  11. L.  Li, L. Gao and J. Xue. Memory coloring: a compiler approach for automatic scratchpad memory management. In 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) , pages 329 -- 338, Saint Louis, Missouri, 2005. (PDF)

  12. L. Li and J. Xue. A trace-based binary compilation framework for energy-aware computing. In ACM SIGPLAN/SIGBED 2004 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04) , pages 95 -- 106, Warshington, DC, 2004. (PDF)

  OO Languages: Analysis and Optimisation

  1. Yi Lu, John Potter and Jingling Xue. Ownership Downgrading for Ownership Types In The Seventh Asian Symposium on Programming Languages and Systems (APLAS'09) , Seoul, 2009. (PDF)

  2. Y. Lu, J. Potter and J. Xue. Validity Invariants and Effects. In 21st European Conference on Object-Oriented Programming (ECOOP'07), pages 202 -- 226, Berlin, 2007. (PDF)

  3. J. Xue, P. Nguyen and J. Potter. Interprocedural Side-Effect Analysis for Incomplete Object-Oriented Software Modules. Journal of Systems and Software, 80(1):92-105, 2007.

  4. P. Nguyen and J. Xue. Interprocedural side-effect analysis for Java programs in the presence of dynamic class loading. In 28th Australasian Computer Science Conference (ACSC'05) , pages 9 -- 18, Newcastle, Australia, 2005. (Best Paper Award)

  5. J. Xue and P. Nguyen. Completeness analysis for incomplete object-oriented programs. In 2005 International Conference on Compiler Construction (CC'05), Edinburgh, UK, 2005. (PDF)

  6. P. Nguyen and J. Xue. Strength Reduction for Loop-Invariant Types. In 27th Australasian Computer Science Conference (ACSC'04) , Dunedin, New Zealand, 2004. (Best Student Paper Award)

  Parallelising Compiler Techniques

  1. Duo Liu, Zili Shao, Meng Wang, Minyi Guo and Jingling Xue. Optimal Loop Parallelization for Maximizing Iteration-Level Parallelism. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'09), Grenoble, 2009. (PDF)

  2. J. Xue, M. Guo and D. Wei. Improving the Parallelism of Iterative Methods by Aggressive Loop Fusion. Journal of Supercomputing, 43(2):147-164, 2008.

  3. L.  Pan, J. Xue, M. Lai, M. Dillencourt and L. Bic. Toward Automatic Data Distribution for Migrating Computations. In 2007 International Conference on Parallel Processing (ICPP'07), Xian, 2007. (PDF)

  4. J. Xue. Aggressive loop fusion for improving locality and parallelism of iterative methods. In 3rd International Symposium on Parallel and Distributed Processing and Applications (ISPA'05) , pages 224 -- 238, Nanjing, China, 2005. (Postscript)

  5. J. Xue and W. Cai. Time-minimal tiling when rise is larger than zero. Parallel Computing, 28(6):915--939, 2002. (Postscript)

  6. P. Lenders and J. Xue. Eigenvectors-based parallelisation of nested loops with affine dependences. Parallel Algorithms and Applications, 17(3):227--248, 2002. (Postscript)

  7. P. Tang and J. Xue. Generating efficient tiled code for distributed memory machines. Parallel Computing, 26(11):1369--1410, 2000. (Postscript)

  8. J. Xue. Loop Tiling for Parallelism. Kluwer Academic Publishers, Boston, August 2000.