AVR Architecture: Slide 47

Memory Access Instructions

The AVR is a RISC architecture. Only load/store instructions access data memory (SRAM).

LDD Rd,Y+q	10q0 qq0d dddd 1qqq	Rd = SRAM[r29:r28 + q]
STD Rd,Y+q	10q0 qq0d dddd 1qqq	SRAM[r29:r28 + q] = Rd

Note the use of the pair of 8-bit registers r28 and r29 as a 16 bit value.

This allows 64k of data space to be addressed by this instruction - ATmega64 has 4k of SRAM.

Special purpose registers (e.g. RAMPY) allow a 24-bit address to formed - only relevant if you have external memory.