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Exercise: MyInt module (cont) 

# General structure of a Makefile
definitions

target: dependencies
	commands

  • definitions define variables (optional)
  • target is the name of the object (usually an executable or .o file) you wish to make
    • can have multiple targets
  • dependencies are the files that the object depends on
    • usually a list of .c, .h, .o files
  • commands is a list of instructions that will make the target
    • usually a compilation
    • each command should be preceded by a tab