Advanced Operating Systems   COMP9242 2002/S2

UNSW

Printer-Friendly Version Administration                - Notices - Course Intro - Consultations # On-line Survey (closed) - Survey Results   Work - Lectures - Milestone 0 - Project Admin - Project Spec - Project FAQ - Exam   Documentation - ASysT Lab - L4 source browser - Sulima ISA Simulator - R4x00 ISA Summary  - MIPS R4700 Reference - MIPS R4000 User Manual  - Network Driver - GT64111   Related Info - Aurema OS Prize - OS Hall of Fame   History - 2000 - 1999 - 1998   Staff - Gernot Heiser (LiC)

L4 Threads A thread is the basic active entity (unit of execution and scheduling). Threads communicate via message-passing IPC. Each thread has a register set (IP, SP, user-visible registers, processor state) an associated task/address space a page fault handler (pager) this is a thread which receives page faults (via IPC) an exception handler (dependent on architecture) this is a thread which receives exceptions (via IPC) preempters (not implemented) tread which receives preemption messages scheduling parameters (priority, time slice) .