School of Computer Science & Engineering
University of New South Wales
Advanced Operating Systems
COMP9242 2002/S2
Next: TLB Issues
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- TLB is a cache for page table entries.
- Can be:
- hardware loaded, transparent to OS, or
- software loaded, maintained by OS.
- Can be:
- split, instruction and data TLBs, or
- unified.
- Some architectures (MIPS, IA-64) use a hierarchy of TLBs:
- Top-level TLB is hardware-loaded from lower levels.
- Transparent to OS.
Gernot Heiser
2002-08-15