Advanced Operating Systems   COMP9242 2002/S2

UNSW

Printer-Friendly Version Administration                - Notices - Course Intro - Consultations # On-line Survey (closed) - Survey Results   Work - Lectures - Milestone 0 - Project Admin - Project Spec - Project FAQ - Exam   Documentation - ASysT Lab - L4 source browser - Sulima ISA Simulator - R4x00 ISA Summary  - MIPS R4700 Reference - MIPS R4000 User Manual  - Network Driver - GT64111   Related Info - Aurema OS Prize - OS Hall of Fame   History - 2000 - 1999 - 1998   Staff - Gernot Heiser (LiC)

Address Space Usage vs. TLB Coverage Each TLB entry maps one virtual page. On TLB miss, reloaded from page table (PT), which is in memory. Some TLB entries need to map page table. E.g. 32-bit page table entries, 4kb pages. One PT page maps 4Mb. Traditional UNIX process has 2 regions of allocated virtual address space: low end: text, data, heap, high end: stack. ==> 2-3 PT pages are sufficient to map most address spaces. Sparse address space use ties up PT entries