[CSE]  Advanced Operating Systems 
  COMP9242 2002/S2  		UNSW
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Next: Cache access Up: 03-cache Previous: Caching

Cache organisation


  • Data transfer unit between registers and cache \(\leq1\) word (1-8B)
  • Date transfer unit between cache and RAM is cache line,
    typically 16-32 bytes, sometimes 128 bytes and more.
  • Line is unit of storage allocation in cache.
  • Each line has associated control info:
    • valid bit,
    • modified bit,
    • tag.
  • Cache improves memory access by:
    • absorbing most reads (increases bandwidth, reduces latency),
    • making writes asynchronous (hides latency),
    • clustering reads and writes (hides latency).


Gernot Heiser 2002-08-15