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School of Computer Science & Engineering
University of New South Wales
 Advanced Operating Systems 
 COMP9242 2002/S2 

Microkernel Implementation

• Overview of main features of L4 implementation:
  • data structures,
  • algorithms.
• Based on MIPS implementation (assembler kernel by Elphinstone)
• These notes are very brief, they are complemented by:
  • L4/MIPS source code[L4M99],
  • ``Inside L4/MIPS''[Hei00]

MIPS address space

L4 physical memory map

Virtual TCB Array:

• Fast TCB location (macros.h:tid2tcb).

Two TCBs per (4kb) page:

• per-thread kernel stack
  • fast context switch;
• kernel stack in TCB
  • locality.

TCB layout

	0:	struct tcb *sndq_end, *wakeup_link, *busy_link,
		*int_link;
	1:	unsigned long wfor; struct tcb *sndq_start;
		unsigned long stack_pointer; udw_t asid;
	2:	void *gpt_pointer; unsigned long myself;
		unsigned int fine_state, timeout; long recv_desc;
	3:	struct tcb *present_next, *child_task;
		uhw_t rem_timeslice, timeslice;
		ub_t mcp, bpad1, ctsp, tsp;
	4:	long wakeup;
		struct tcb *soon_wakeup_link,
		*late_wakeup_link, *sndq_next;
	...

Kernel data layout

	0:	dw_t stack_bottom;
		udw_t s0_save, *free_asid_list;
		tcb_t *wakeup_list;
		...

Kernel stack:

Exception stack as set up by general exception handler (prior to k_ipc).

Kernel stack...

Sender's kernel stack when switching to receiver (end of deliver).

Kernel stacks & TCBs

Accessing receiver's data during long IPC

• All IPC processing is done in sender's context.
  • Sender's address space accessible (but may get TLB misses).
• To access receiver's data (for receive descriptor, strings):
  • shift all receiver addresses into temporary mapping area
  • TMA located in kernel-reserved address range (),
  • TLB miss handler recognises TMA address range
    • faults handled by translating receiver page table entries,
    • if not mapped, invoke receiver's pager.
  
• Implies handling user page faults in kernel mode.

Page fault handling

• TLB misses in user mode invoke fast TLB miss hander
  • reload from page table
• Misses in kernel mode, or on unmapped user memory:
  • invoke the slow TLB miss handler, exc_tlbs, exc_tlbl.
• Deals with three kinds of misses:
  
  

  	user page fault ==> invoke pager
  	window fault ==> look up receiver's PT & remap
  	kernel TLB miss on TCB array ==> allocate TCB

• first can happen any time, last two only in kernel mode
  • Need to be able to invoke user's pager during IPC.
  • Kernel ``fakes'' exception stack to invoke pager
    • as per IPC syscall (using k_ipc code)
  • ``EPC'' is restart routine.