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Next: Partial store ordering
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Subsections
- Stores to write buffer hide memory latency.
- Loads read from write buffer if possible.
- Stores are guaranteed to occur in FIFO order.
CPU 0 |
store |
r1, adr1 |
load |
r2, adr2 |
CPU 1 |
store |
r1, adr2 |
load |
r2, adr1 |
- Both CPUs may read old values!
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void lock (volatile lock_t *l) { |
l-> status[MYSELF] = LOCKED; |
while (l-> status[OTHER] == LOCKED) { |
if (l-> turn != MYSELF) { |
l-> status[MYSELF] = !LOCKED; |
while (l-> turn == OTHER) ; |
l-> status[MYSELF] = LOCKED; |
} } } |
- Need hardware support for synchronisation, e.g.:
- atomic swap,
- test&set,
- load-linked & store-conditional (LL&SC),
- memory barriers.
- Stall pipeline and drain (& bypass) write buffer.
Next: Partial store ordering
Up: 10-smp
Previous: Other Memory Models
Gernot Heiser
2002-10-11
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