[CSE]  Advanced Operating Systems 
 COMP9242 2002/S2 
UNSW

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Subsections

How to Roll Your Own Tagged TLB and Caches

Context switch with untagged TLB:

 $.$
load translation table base register to replace page table
 $.$
flush instruction TLB
 $.$
flush data TLB
 $.$
flush instruction cache (if virtual)
 $.$
flush data cache (if virtual)
==>
High overhead

Simulating TLB tags by segmentation:

segment

Segment registers as ASID tags:

  • Fill all segment registers with process' ASID
  • Problem if flat VAS is only 32-bit (Pentium)
  • Partial solution[Lie95]:
    • split AS into large (3GB) and small area
    • small area split into smaller (128MB) slots
    • put small processes into a slot
    • can do fast context switches between one large and all small processes

On non-segmented architecture (StrongARM)

  • StrongARM SA-1100 is a high-performance low-power processor
  • Designed for embedded applications
  • Some less attractive features (for multitasking):
    • virtually indexed, virtually tagged caches,
    • untagged, hardware-loaded TLB.

ARM Page Tables

  • Top-level PT entry can:
    • map a 1MB section;
      protection with section granularity,
    • point to a second-level PT.
  • Second-level PT entry can:
    • map a 64kB large page,
    • map a 4kb small page.
    Protection with 1/4 page granularity.
  • Each page or section is tagged with a domain id

ARM Domains

Additional access-control feature:

  • 16 different domains,
  • domain access control register (DACR) defines accessibility for each:
    • no access
    • access according to page permission bits
    • access irrespective of page permission bits

How to avoid flushing?

  • Can avoid flushes if no overlap of address spaces
  • How????
  • Two-part approach[WH00]:
    • delay flushes as long as possible
      in microkernel
    • avoid overlaps as much as possible
      in server

Delaying flushes: Idea

  • Don't change hardware page tables.
  • Have translation table base register point to a
    cache of top-level page table entries (CPD).
  • Use domain IDs as address-space tag.
  • Flush TLB entries and caches when replacing CPD entry.

Caching page directory

cpd

Context switch:

  • Set software PT pointer to reference new context's page table
  • Load DACR to:
    • ``access according to page permission bits''
      for new context's domain,
    • ``no access'' for other domains
  • Go!
No flushes required as long as have separate domain per context.

Cache replacement

  • Domains ensure that CPD entries belonging to wrong context
    raise domain fault exception.
  • Handled by:
    • replacing CPD entry
    • flushing TLBs and caches
    ==> flush only in case of actual collision.
  • Also need to flush if recycling domains.

Avoiding overlap

  • Server to allocate process data & stack at unique addresses
    ==> mini-SASOS (single-address-space OS)
  • Need to use separate domains for shared (text). segments
  • Aliasing still a problem.


next up previous
Next: Bibliography Up: 14-hot Previous: The Return of the
Gernot Heiser 2002-11-07