COMP9244 Provisional Course Introduction

(Comparison of Contemporary Processor Architectures from the Software Point of View)
	Proc. Architectures: S/W View COMP9244 2006/S1	UNSW CRICOS Provider Number: 00098G

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Administration
- Notices
- Course Outline
# On-line Survey

Work
- Seminar Schedule

History
- 2004
- 2003

Staff
- Gernot Heiser (LiC)

Provisional Course Introduction

Status

This course has been approved by the Teaching Committee of the School. Approval by the Faculty is pending.

The course will be offered in S1/2003 with Gernot Heiser as Lecturer in Charge. It is aimed at students enrolled in a Research Master's or PhD program in the areas of operating systems and compilers. It will be delivered as a mixture of lectures and student seminars. The course has 6 UoC.

Since the course has not yet been approved by the faculty (for reasons out of our control) you cannot officially enrol in it yet. Please mail the LiC if you want to take the course.

Handbook entry

Examination of contemporary computer architectures, comparing and contrasting their software-visible features (caches, memory management unit, pipelining and instruction-level parallelism, instruction set architecture, register files). Examination of the effect of these features on the design and implementation of operating systems, compilers, run-time systems, etc. Discussion of software techniques for dealing with these architectural features.

The course is aimed at providing research students in the fields of systems and compilers with the relevant advanced architecture background and an idea of where architectures are likely to head in the next 5-10 years.

Objective

Research students working in compilers, language design, operating systems and embedded systems need to learn more about the features that specifically impact low-level system software. While not necessarily interested in processor design issues, they need to understand the full range of such features, and their combinations, in contemporary processors. And they need to understand the implications these features have on software design. In particular, they should be able to answer questions such as:

How can the software designer abstract over the various instantiations of a particular architectural feature across the range of available architectures, and what software designs will support portability?
What implications do architectural decisions have on program performance and what techniques may be used to obtain maximum performance from a particular processor family?
How likely is a particular approach to be tied to a particular processor family, or to a particular processor model within a family?
What architectural features are available but have not been properly exploited to date? How could they be used?
How are issues like data layout, locks, low-level parallelism, context switching rates, probability of taking if vs. else branches, working sets, etc., affect performance or power consumption on a specific architecture?
What are the likely developments in the next few years? For example, will caches grow at all levels or will there be more levels? Will associativity increase or decrease?

The proposed course is meant to address these issues. It is and advanced-level architecture course which is, however, not primarily aimed at students doing (or intending to do) research in computer architecture. Instead it targets research students in related areas who need to accept the architecture as given, but need to understand what they can do with it.

In summary, the introduction of this course is seen as an important part of the strategy to build up a world-class research group in the general ``systems'' area at UNSW.

Specific topics covered

Instruction set architecture:: RISC vs CISC, VLIW, ILP, addressing modes, synchronisation primitives, pipelining, issue slots, load and branch penalties, delay slots, out-of-order execution, EPIC, SIMD instructions, predication, status flags
Cache memory architecture:: virtual/physical, split/unified, associativity, latency, coherency, write buffers, store order...; software cache management (colouring)
MMU design:: page sizes, TLB size and associativity, split/unified TLBs, TLB tagging, segmentation, support for sharing, hardware vs software reload, multi-level TLBs, pinning of entries; software algorithms and data structures (e.g., TLB caches)
Multiprocessors and interconnection architecture:: SMP, NUMA, single-chip multiprocessors, symmetric multithreading; inter-processor communication mechanisms and latencies

Assessment

Students will present one or two seminars. They will also submit a written report on the topic of their seminar. The report will be able to take into account feedback received at or after the seminar(s), as well as material covered later in the course. Assessment (using standard UNSW grades) will be based on the seminar(s) as well as the report. Key assessment criteria will be the quality of the (oral and written) presentation and, in particular, the depth and degree of insight demonstrated in the seminar(s) and the report.

Last modified: 24 Dec 2002.