COMP9244 2003 Course Introduction

(Comparison of Contemporary Processor Architectures from the Software Point of View)
	Proc. Architectures: S/W View COMP9244 2006/S1	UNSW CRICOS Provider Number: 00098G

Printer-Friendly Version

Administration
- Notices
- Course Outline
# On-line Survey

Work
- Seminar Schedule

History
- 2004
- 2003

Staff
- Gernot Heiser (LiC)

Course Introduction

Objective

Research students working in compilers, language design, operating systems and embedded systems need to learn more about the features that specifically impact low-level system software. While not necessarily interested in processor design issues, they need to understand the full range of such features, and their combinations, in contemporary processors. And they need to understand the implications these features have on software design. In particular, they should be able to answer questions such as:

How can the software designer abstract over the various instantiations of a particular architectural feature across the range of available architectures, and what software designs will support portability?
What implications do architectural decisions have on program performance and what techniques may be used to obtain maximum performance from a particular processor family?
How likely is a particular approach to be tied to a particular processor family, or to a particular processor model within a family?
What architectural features are available but have not been properly exploited to date? How could they be used?
How are issues like data layout, locks, low-level parallelism, context switching rates, probability of taking if vs. else branches, working sets, etc., affect performance or power consumption on a specific architecture?
What are the likely developments in the next few years? For example, will caches grow at all levels or will there be more levels? Will associativity increase or decrease?

This course is meant to address these issues. It is and advanced-level architecture course which is, however, not primarily aimed at students doing (or intending to do) research in computer architecture. Instead it targets research students in related areas who need to accept the architecture as given, but need to understand what they can do with it.

In summary, the introduction of this course is seen as an important part of the strategy to build up a world-class research group in the general ``systems'' area at UNSW.

Specific topics covered

Instruction set architecture:: RISC vs CISC, VLIW, ILP, addressing modes, synchronisation primitives, pipelining, issue slots, load and branch penalties, delay slots, out-of-order execution, EPIC, SIMD instructions, predication, status flags
Cache memory architecture:: virtual/physical, split/unified, associativity, latency, coherency, write buffers, store order...; software cache management (colouring)
MMU design:: page sizes, TLB size and associativity, split/unified TLBs, TLB tagging, segmentation, support for sharing, hardware vs software reload, multi-level TLBs, pinning of entries; software algorithms and data structures (e.g., TLB caches)
Multiprocessors and interconnection architecture:: SMP, NUMA, single-chip multiprocessors, symmetric multithreading; inter-processor communication mechanisms and latencies

Structure

The course will be run as a seminar series, consisting of two parts:

advanced architecture concepts, and their effects on software;
advanced architecture implementations, i.e. case studies of modern commercial processor architectures and how they deal with the issues discussed in the first part.

Each student will present two seminars, with one topic taken from each part of the course. The seminars will be presented to the class and critiqued by the presenters' peers. The critique will cover both presentation as well as content of the seminar (e.g. misrepresenations/misunderstandings or material omitted).

After their seminar, each student has a week to complete a report on the topic area. Students are strongly encouraged to have a complete draft of the report ready for their seminar, and use the feedback from their peers (and lecturer) for improving the report before submitting it.

Assessment

The final assessment will be a straight sum of five component marks: two seminars, two reports and class participation. Each seminar will be worth 20 marks, and reach report will be worth 25 marks, while class participation will be worth 10 marks.

Key assessment criteria will be the quality of the (oral and written) presentation and, in particular, the depth and degree of insight demonstrated in the seminar(s) and the report. An important consideration for the seminar is how much the presenter's peers will have learnt. Seminars will be assessed by the LiC, with advise/feedback from the students in the course. That feedback will be in the form of a discussion after the seminar, plus an anonymous poll of students (other than the presenter) as to the deserved mark.

Penalty for late reports is one mark lost per day late (seven marks per week).

Plagiarism

Plagiarism in any form will be severely dealt with. Students found to have essentially plagiarised their seminar or report will receive a final mark of zero for the course. Lesser penalties apply in cases where fractions of a report are found to have taken from some source without proper acknowledgement of authorship.

Literature

Much of the information relevant to the first part is contained in:

John L. Hennessy and David A. Patterson: Computer Architecture, a Quantitative Approach. Morgan Kaufmann Publishers, 3^rd edition, 2003.

plus the 22 pages of references cited there.

Information relevant to the second part is only partially availabel from the book, but should be available on the Web from manufacturer's sites etc.

Last modified: 31 Mar 2003.