L4 on MIPS R4x00: Release Notes

General Enhancements

Bug Fixes (since version 79)

• Bug: Kernel panics if IDT 79R4600 rev. 2.0 erratum 7 situation occurs.
  The CPU sometimes generates incorrect BVA and EntryHi addresses in a TLBmod exception taken on the second last instruction in a page. Synthesize the correct BVA and jump back to exc_tlbs().

  Fixed, the situation is now handled correctly by synthesizing the correct BVA.

• Bug: Apparently random kernel exceptions during id_nearest().
  id_nearest(SIGMA0_TID) system calls by inner tasks seem to result in the kernel randomly panicking with a probability of several percent.

  Fixed.

• Bug: Hi, Lo registers not preserved across context switches:
  The division/multiplication registers hi, lo are lost across context switches.

  Fixed.

• Bug: Send fpage of size 64:

If a send fpage of size 64 is used nothing gets mapped at all.

Fixed.

Extra (non-standard) features

• Independent send- and receive targets
  L4/MIPS allows to specify the send-to and receive-from thread ids of a single IPC operation independently of each other. Standard L4 only supports combining a send with a closed receive from the same thread.

Restrictions

• The List of known bugs and limitations is being updated as we find them.