Hui Guo received her Bachelor’s and Master’s degrees in Electrical and Electronic Engineering at the Anhui University in China and PhD in Electrical and Computer Engineering at the University of Queensland in Australia. Prior to joining the University of New South Wales to start her academic career, she had worked in several companies/organizations in Canada, for large information and e-commerce systems development.

 

She is now a lecturer in the School of Computer Science and Engineering at the University of New South Wales. She is a member of IEEE and has serviced as the TCP member for a number of international conferences.

 

 

Contact:

 

Dr. Hui Guo

Room 501F, Level 5, K-17

School of Computer Science and Engineering

UNSW, NSW 2052, Australia

Phone: +61 2 9385 7136

Email: huig@cse.unsw.edu.au

 

 

 

Research Interests:

 

  • ASIP Design
    • Design Methodology
    • Multi-pipeline ASIP Design
  • System Level Pipelining
    • Scheduling and Partitioning
    • Power Reduction
    • Dynamic Pipeline Design
  • Low Power Logic Circuits Design
    • Dynamic Power Reduction
    • Performance improvement
  • Embedded System Design
    • Design methodology
    • Customization Techniques

 

 

 

Research Fundings:

 

  • Sri Parameswaran, Hui Guo, A. Ignjatovic, Design of Highly Secure Embedded Systems Using Modern Architecture Processors, 2007 UNSW Goldstar Award
  • Hui Guo, An Approach to Enhance Performance of Multi-Pipe Application Specific Instruction-Set Processor Systems with Large Memory, Faculty Research Grant (FRG), 2007
  • A. Ignjatovic, H. Guo, et al. Computer Simulations, Research Infrastructure Block Grant (RIBG), 2005
  • Hui Guo, System Level Pipelining and Applications, Faculty Research Grant Program (FRG), 2005
  • Hui Guo, Sri Parameswaran, Embedded Systems, Research Infrastructure Block Grant (RIBG), 2003

 

 

Publications:

 

  • Mei Hong, Hui Guo. Design of Multi-Service Smart Card Systems with High Security and Performance, International Journal of Security and Its Applications, Vol. 3, No. 1, 2009
  • Ji Gu, Hui Guo. A Segmental Bus-Invert Encoding for Instruction Data Bus Switching Reduction, The 2009 International Symposium of Circuits and Systems, Taipei, Taiwan, 2009 (ISCAS  2009)
  • Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic. HMP-ASIPs: Heterogeneous Multi-Pipeline Application Specific Instruction-set Processors. IET Computers & Digital Techniques (Journal of the Institution of Engineering and Technology), Vol.3, Issue 1, Pages:94-108,  2009
  • Yu Zhou, Hui Guo. Application Specific Low Power ALU Design, The 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008,, Shanghai, China, Pages:214-220
  • Mei Hong, Hui Guo and Bin Luo. Security Design for Networked Multi-Service Smart Card Systems, The Second International Conference on Future Generation Communication and Networking (FGCN 2008), 2008, Sanya, China, Pages:299-304
  • Swarnalatha Radhakrishnan, Sri Parameswaran, Hui Guo. Heterogeneous Multi-pipeline ASIP – Design and Implementation, VDM Verlag , 2008
  • Hui Guo, Application Specific Gray Code Encoding for Instruction Memory Address Bus Switching Reduction, In proceedings of  VLSI-SoC, 2008, Greece.
  • Daming Zhang, Hui Guo, Bin Luo. An Algorithm for Estimating Number of Components of Gaussian Mixture Model Based on Penalized Distance, In proceedings of ICNNSP’08, 2008, June 7-11, ZhengJiang, China
  • Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic. Application Specific Forwarding Network and Instruction Encoding for Multi­pipe ASIPs. In proceedings of CODES+ISSS’06, 2006
  • Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran. Customization of Application Specific Heterogeneous Mult-Pipeline Processors, DATE 2006.
  • Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran. n-pipe: Application Specific Heterogeneous Mult-Pipeline Processor Design, The Workshop on Application Specific Processors, Sept. 2005
  • Hui Guo, Sri Parameswaran. Balancing System Pipelines with Stage Voltage Scaling. In Proceedings of International Symposium on VLSI, May 2005.
  • Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran. Dual-pipeline heterogeneous ASIP Design, In proceedings of CODES+ISSS’04, Sept. 2004
  • Hui Guo, Paramewaran, S. Unrolling loops with indeterminate loop counts in system level pipelines. Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific, 10-13 Feb. 1998 . Page(s): 99 –104
  • Parameswaran, S.; Hui Guo; Power reduction in system level pipelines, Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific , 10-13 Feb. 1998. Page(s): 545 –550
  • Parameswaran, S.; Hui Guo. Power consumption in CMOS combinational logic blocks at high frequencies. Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific , 28-31 Jan. 1997. Page(s): 195 –200
  • Parameswaran, S.; Hui Guo.  Partitioning of System Level Pipelines. The 14th Australia Microelectronics Conference (MICRO’97), Oct. 1997. Page(s): 233-238
  • Parameswaran, S.; Hui Guo. Extracting Higher Performance/Power in Combinational CMOS Circuits. PATMOS’96 Sixth International Workshop, 1996. Page(s): 93-102
  • Hui Guo; Paramewaran, S . System Level Pipelining. Asia Pacific Conference on Hardware Description Languages (APCHDL) Conference, 1996. Page(s): 28-33

 

 

Teaching Areas:

 

  • Computer Architectures, COMP3221 
  • Digital System Structures, COMP9022
  • Microprocessors and Interfacing, COMP9032