Hui Guo received the Bachelor and Masters degrees in Electrical and Electronic Engineering at Anhui University in China and PhD in Electrical and Computer Engineering at the University of Queensland in Australia. Prior to joining the University of New South Wales to start her academic career, she had worked in several companies/organizations in Canada, for large information and e-commerce systems development.

 

She is now a senior lecturer and the program director of Computer Engineering in the School of Computer Science and Engineering at the University of New South Wales. She is a member of IEEE and has serviced as the TCP member for a number of international conferences.

 

 

Contact:

 

Dr. Hui Guo

Room 501F, Level 5, K-17

School of Computer Science and Engineering

UNSW, NSW 2052, Australia

Phone: +61 2 9385 7136

Email: huig@cse.unsw.edu.au

 

 

 

Research Interests:

 

  • ASIP Design
    • Design Methodology
    • Multi-pipeline ASIP Design
  • System Level Pipelining
    • Scheduling and Partitioning
    • Power Reduction
    • Dynamic Pipeline Design
  • Low Power Logic Circuits Design
    • Dynamic Power Reduction
    • Performance improvement
  • Embedded System Design
    • Design methodology
    • Customization Techniques

 

 

 

Research Fundings:

 

  • Sri Parameswaran, Hui Guo, A. Ignjatovic, Design of Highly Secure Embedded Systems Using Modern Architecture Processors, 2007 UNSW Goldstar Award
  • Hui Guo, An Approach to Enhance Performance of Multi-Pipe Application Specific Instruction-Set Processor Systems with Large Memory, Faculty Research Grant (FRG), 2007
  • A. Ignjatovic, H. Guo, et al. Computer Simulations, Research Infrastructure Block Grant (RIBG), 2005
  • Hui Guo, System Level Pipelining and Applications, Faculty Research Grant Program (FRG), 2005
  • Hui Guo, Sri Parameswaran, Embedded Systems, Research Infrastructure Block Grant (RIBG), 2003

 

 

Recent Publications:

 

  • Ji Gu, Hui Guo. DLIC: Decoded Loop Instructions Caching For Energy-Aware Embedded Processors, accepted by ACM Transactions on Embedded Computing Systems.
  • Chuan He, Xiaomin Zhu, Hui Guo, and Jianqing Jiang. Rolling-Horizon Scheduling for Energy Constrained Distributed Real-Time Embedded Systems, Journal of Systems Software, Volum 85, Issue 4, 2012
  • Ji Gu and Hui Guo. Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems, International Journal of Handheld Computing Research, 2(4), 2011, page 42-58
  • Ji Gu, Hui Guo and Patrick Lee. An On-Chip Instruction Cache Design with One-bit Tag for Low Power Embedded Systems, Microprocessors and Microsystems, 35, 2011, Pages 382-391
  • Hui Guo. A Structural Customization Approach for Low Power Embedded Systems Design, IEEE/ACM International Conference on Green Computing and Communications, 2010, 237-244
  • Ji Gu and Hui Guo. Enabling Large Decoded Loop Instruction Caching for Energy-Aware Embedded Processors, CASES, 2010
  • Hui Guo, Sri Parameswaran, Shifted Gray Encoding to Reduce Instruction Memory Address Bus Switching for Low Power Embedded Systems, Journal of Systems Architecture, Volume 56, Issues 4-6, April-June 2010, Pages 180-190.
  • Ji Gu and Hui Guo. An Energy Efficient Instruction Prefetching Scheme for Embedded Processors, The 2010 International Conference on Ubiquitous Computing and Multimedia Applications, 2010.
  • Mei Hong and Hui Guo. FEDTIC: A Security Design for Embedded Systems with Insecure External Memory, The 2010 International Conference on Ubiquitous Computing and Multimedia Applications, 2010.
  • Ji Gu, Hui Guo and Patrick Lee. ROBTIC: An On-Chip Instruction Cache Design for Low Power Embedded Systems, The 15th IEEE International Conference on Embedded and Real-Time Computing Systems and  Applications (RTCSA 2009), Beijing, China, Aug. 24-26, 2009
  • Yu Zhou, Hui Guo and Ji Gu. Register File Customization for Low Power Embedded Processors. The 2nd IEEE International Conference on Computer Science and Information Technology (IEEE ICCSIT 2009)
  • Ji Gu, Hui Guo. An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction, EURASIP Journal on Embedded Systems, vol. 2009
  • Mei Hong, Hui Guo. Design of Multi-Service Smart Card Systems with High Security and Performance, International Journal of Security and Its Applications, Vol. 3, No. 1, 2009
  • Ji Gu, Hui Guo. A Segmental Bus-Invert Encoding for Instruction Data Bus Switching Reduction, The 2009 International Symposium of Circuits and Systems, Taipei, Taiwan, 2009 (ISCAS  2009)
  • S. Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic. HMP-ASIPs: Heterogeneous Multi-Pipeline Application Specific Instruction-set Processors. IET Computers & Digital Techniques (Journal of the Institution of Engineering and Technology), Vol.3, Issue 1, Pages:94-108,  2009
  • Yu Zhou, Hui Guo. Application Specific Low Power ALU Design, The 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008,, Shanghai, China, Pages:214-220
  • Mei Hong, Hui Guo and Bin Luo. Security Design for Networked Multi-Service Smart Card Systems, The Second International Conference on Future Generation Communication and Networking (FGCN 2008), 2008, Sanya, China, Pages:299-304
  • S. Radhakrishnan, Sri Parameswaran, Hui Guo. Heterogeneous Multi-pipeline ASIP – Design and Implementation, VDM Verlag , 2008
  • Hui Guo, Application Specific Gray Code Encoding for Instruction Memory Address Bus Switching Reduction, In proceedings of  VLSI-SoC, 2008, Greece.
  • Daming Zhang, Hui Guo, Bin Luo. An Algorithm for Estimating Number of Components of Gaussian Mixture Model Based on Penalized Distance, In proceedings of ICNNSP’08, 2008, June 7-11, ZhengJiang, China
  • S. Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic. Application Specific Forwarding Network and Instruction Encoding for Multi­pipe ASIPs. In proceedings of CODES+ISSS’06, 2006
  • S. Radhakrishnan, Hui Guo, Sri Parameswaran. Customization of Application Specific Heterogeneous Mult-Pipeline Processors, DATE 2006.
  • S. Radhakrishnan, Hui Guo, Sri Parameswaran. n-pipe: Application Specific Heterogeneous Mult-Pipeline Processor Design, The Workshop on Application Specific Processors, Sept. 2005
  • Hui Guo, Sri Parameswaran. Balancing System Level Pipelines with Stage Voltage Scaling. In Proceedings of IEEE Symposium on VLSI, May 2005.
  • S. Radhakrishnan, Hui Guo, Sri Parameswaran. Dual-pipeline heterogeneous ASIP Design, In proceedings of CODES+ISSS’04, Sept. 2004

 

 

Teaching Areas:

 

  • Computer Architectures, COMP3211
  • Digital System Structures, COMP9022
  • Microprocessors and Interfacing, COMP9032
  • Digital Circuits and Systems, COMP3222