Hui  Wu

 

    Lecturer

 

    School of Computer Science and Engineering

    The University of New South Wales, Sydney 2052 

    Office: K17-501D

    Tel:  (02) 93856572

    E-mail: huiw@cse.unsw.edu.au

 

 

 

  Education

·         PhD in Computer Science from National University of Singapore.

 

  Teaching

·         COMP9032: Microprocessors and Interfacing

·     COMP9024: Data Structures and Algorithms

 

  Research

·         Real-Time Embedded Systems

·         Energy-Aware Computing

·         Parallel and Distributed Systems

 

  Selected Publications

  1. Hui Wu, Jaxan Jaffar and Jingling Xue. Instruction Scheduling with Release Times and Deadlines. To appear in the Proceedings of the 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. August 2006, Sydney.
  2. Hui Wu and Sridevan Parameswaran. Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on A Single Processor. To appear in the Proceedings of the 2006 IFIP International Conference on Embedded And Ubiquitous Computing. August 2006, Seoul, Korea.
  3. Hui Wu and Joxan Jaffar. A Fast Algorithm for Two Processor Scheduling with Release Time and Deadline Constraints. SIAM Journal on Computing. To appear.
  4. Hui Wu and Joxan Jaffar.  Two Processor Scheduling with Real Release Times and Deadlines.  The 14th ACM Symposium on Parallel Algorithms and Architectures (SPAA), August 2002, Manitoba, Canada, pp 127-132.
  5. Hui Wu, Wei-Ngan Chin and Joxan Jaffar. An Efficient Distributed Deadlock Avoidance Algorithm for AND Model.  IEEE Transactions on Software Engineering. Vol. 28, No. 1, Jan 2002,  pp 18-29.
  6. Hui Wu and Joxan Jaffar. An Efficient Algorithm for Scheduling Instructions with Deadline Constraints on ILP Processors. The 22nd IEEE Real-Time Systems Symposium (RTSS), London, UK, Dec. 2001, pp 235-242.
  7. Hui Wu, Joxan Jaffar and Roland Yap. A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Machines. The International Conference on Parallel Architecture and Compilation Techniques (PACT). Oct. 2000, Philadelphia, PA, pp 281-290.
  8. Hui Wu, Joxan Jaffar and Roland Yap. Instruction Scheduling with Timing Constraints on A Single RISC Processor with 0/1 Latencies. The Sixth International Conference on Principles and Practice of Constraint Programming (CP). Sept. 2000, Singapore, pp 457-469 .