2010

1. Hongtao Yu, Zhaoqing Zhang, Xiaobing Feng, Wei Huo and Jingling Xue. Level by Level: Making Flow- and Context-Sensitive Pointer Analysis Scalable for Millions of Lines of Code. In 8th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'10) , Toronto, 2010. (PDF)

2. Li Wang, Jingling Xue and Xuejun Yang. Reuse-Aware Modulo Scheduling for Stream Processors. In International Conference on Design, Automation and Test in Europe (DATE'10) , Dresden, 2010. (PDF)

2009

1. Lian Li, Hui Feng and Jingling Xue. Compiler-directed scratchpad memory management via graph coloring. ACM Transactions on Architecture and Code Optimization (TACO), 6(3), 2009. (PDF)

2. Yi Lu, John Potter and Jingling Xue. Ownership Downgrading for Ownership Types. In The Seventh Asian Symposium on Programming Languages and Systems (APLAS'09) , Seoul, 2009. (PDF)

3. Duo Liu, Zili Shao, Meng Wang, Minyi Guo and Jingling Xue. Optimal Loop Parallelization for Maximizing Iteration-Level Parallelism. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'09), Grenoble, France, 2009. (PDF)

4. Lin Gao, Lian Li, Jingling Xue and Tin-Fook. Ngai. Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction. In 2009 International Conference on Compiler Construction (CC'09), pages 78 -- 93, York, UK, 2009. (PDF)

5. Xuejun Yang, Li Wang, Jingling Xue, Yu Deng and Ying Zhang. Comparability Graph Coloring for Optimizing Utilization of Stream Register Files in Stream Processors. In 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'09) , pages 111 -- 120, North Carolina, 2009. (PDF)

2008

1. Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik. ACS: an Addressless Configuration Support for Partial Reconfigurations. In IEEE International Conference on Field-Programmable Technology (FPT08) , pages 161 -- 168, Taiwan, 2008. (PDF)

2. Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li and Guibin Wang. Exploiting Loop-Dependent Stream Reuse for Stream Processors. In 17th International Conference on Parallel Architectures and Compilation Techniques (PACT'08) , pages 28 -- 37, Toronto, 2008. (PDF)

3. Lin Gao, Quan Hoang Nyugen, Lian Li, Jingling Xue and Tin-Fook Ngai. Thread-Sensitive Modulo Scheduling for Multicore Processors. In 2008 International Conference on Parallel Processing (ICPP'08), pages 132 -- 140, Portland, Oregon, 2008. (PDF)

4. Anderson Kuei-An Ku, Jenny Yi-Chun Kuo and Jingling Xue. A Gather/Scatter Hardware Support for Efficient Fast Fourier Transform. In 13th Asia-Pacific Computer Systems Architecture Conference (ACSAC'08), pages 1 -- 8, Taiwan, 2008.

5. Anderson Kuei-An Ku, Jenny Yi-Chun Kuo and Jingling Xue. Hardware Support for Efficient Sparse Matrix Vector Multiplication. In 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC-08) , pages 37 -- 43, Shanghai, 2008.

6. L. Wang, X. Yang, J. Xue, Y. Deng, X. Yan, T. Tang and Q. H. Nguyen. Optimizing Scientific Application Loops on Stream Processors. In ACM SIGPLAN/SIGBED 2008 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), pages 161 -- 170, Tucson, AZ, 2008. (PDF)

7. P. Lenders and J. Xue. Factorization of Singular Integer Matrices. Linear Algebra and its Applications, 428(4): 1046-1055, 2008. (PDF)

8. B. Scholz, B. Burgstaller and J. Xue. Minimal Placement of Bank Selection Instructions for Partitioned Memory Architectures. ACM Transactions on Embedded Computing Systems (TECS), 7(2), 2008. (PDF)

9. J. Xue, M. Guo and D. Wei. Improving the Parallelism of Iterative Methods by Aggressive Loop Fusion. Journal of Supercomputing, 43(2):147-164, 2008. (PDF)

2007

1. L. Gao, L. Li, J. Xue and T.K  Ngai. Loop Recreation for Thread-Level Speculation. In 2007 International Conference on Parallel and Distributed Systems (ICPADS'07), Hsingchu, Taiwan, 2007. (PDF)

2. L. Li, H. Wu, H. Feng and J. Xue. Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. In 12th Asia-Pacific Computer Systems Architecture Conference (ACSAC'07), pages 63 -- 74, Seoul, Korea, 2007.

3. L.  Pan, J. Xue, M. Lai, M. Dillencourt and L. Bic. Toward Automatic Data Distribution for Migrating Computations. In 2007 International Conference on Parallel Processing (ICPP'07), Xian, China, 2007. (PDF)

4. Y. Lu, J. Potter and J. Xue. Validity Invariants and Effects. In 21st European Conference on Object-Oriented Programming (ECOOP'07), pages 202 -- 226, Berlin, 2007. (PDF)

5. L. Li, Q. H. Nguyen and J. Xue. Scratchpad Allocation for Data Aggregates in Superperfect Graphs. In ACM SIGPLAN/SIGBED 2007 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), pages 207 -- 216, San Diego, 2007. (PDF)

6. X. Vera, B. Lisper and J. Xue. Data Cache Locking for Tight Timing Calculations. ACM Transactions on Embedded Computing Systems (TECS), 7(1), 2007. (PDF)

7. J. Xue, P. Nguyen and J. Potter. Interprocedural Side-Effect Analysis for Incomplete Object-Oriented Software Modules. Journal of Systems and Software, 80(1):92-105, 2007.

8. L. Li and J. Xue. Trace-based Leakage Energy Optimisations at Link Time. Journal of Systems Architecture, 53(1):1--20, 2007.

2006

1. B. Scholz, B. Burgstaller and J. Xue. Minimizing Bank Selection Instructions for Partitioned Memory Architectures}. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'06), pages 201 -- 211, Seoul, Korea, 2006. (PDF)

2. B.  Ye, M. Guo and J. Xue. CoopStream: A Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks. In 2006 International Conference on Parallel Processing (ICPP'06), pages 577 -- 584, Columbus, Ohio, USA, 2006. (PDF)

3. H. Wu, J. Jaffar and J. Xue. Instruction Scheduling with Release Times and Deadlines on ILP Processors. In 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), pages 51 -- 60, Sydney, Australia, 2006. (PDF)

4. L. Li and J. Xue. Trace-based Data Cache Leakage Reduction at Link Time. In 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC'06), pages 175 -- 188, Shanghai, China, 2006.

5. J. Xue and Q. Cai. A lifetime optimal algorithm for speculative PRE. ACM Transactions on Architecture and Code Optimization (TACO), 3(2):115-155, 2006. (PDF)

6. J. Xue, Q. Cai and L. Gao. Partial dead code elimination on predicated code regions. Software -- Practice and Engineering, 36(15): 1655-1685, 2006.

7. J. Xue and J. Knoop. A Fresh Look at PRE as a Maximum Flow Problem. In 2006 International Conference on Compiler Construction (CC'06), pages 139--154, Vienna, Austria, 2006. (PDF)

2005

1. J. Xue and Q. Huang. Code Tiling: One Size Fits All. In G. T. Yang and M. Guo, editors, High Performance Computing: Paradigm and Infrastructure, Chapter 11, pages 219--240. John Wiley & Sons Inc., 2005.

2. C. Yang, X. Yang and J. Xue. Improving the Performance of GCC by Exploiting IA-64 Architectural Features. In 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC'05) , pages 236 -- 251, Singapore, 2005. (Postscript)

3. J. Xue. Aggressive loop fusion for improving locality and parallelism of iterative methods. In 3rd International Symposium on Parallel and Distributed Processing and Applications (ISPA'05) , pages 224 -- 238, Nanjing, China, 2005. (Postscript)

4. L.  Li, L. Gao and J. Xue. Memory coloring: a compiler approach for automatic scratchpad memory management. In 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) , pages 329 -- 338, Saint Louis, Missouri, 2005. (PDF)

5. J.  Xue, Q. Huang and M. Guo. Enabling loop fusion and tiling for cache performance by fixing fusion-preventing data dependences. In 2005 International Conference on Parallel Processing (ICPP'05), pages 107 - 115, Oslo, Norway, 2005. (PDF)

6. J. Xue and P. Nguyen. Completeness analysis for incomplete object-oriented programs. In 2005 International Conference on Compiler Construction (CC'05), pages 271--286, Edinburgh, UK, 2005. (PDF)

7. P. Nguyen and J. Xue. Interprocedural side-effect analysis for Java programs in the presence of dynamic class loading. In 28th Australasian Computer Science Conference (ACSC'05) , pages 9 -- 18, Newcastle, Australia, 2005 (Best Paper). (PDF)

2004

1. J. Xue and X. Vera. Efficient and accurate analytical modeling of whole-program data cache behavior. IEEE Transactions on Computers, 53(5):547--566, 2004.

2. L. Li and J. Xue. A trace-based binary compilation framework for energy-aware computing. In ACM SIGPLAN/SIGBED 2004 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04) , pages 95 -- 106, Warshington, DC, 2004. (PDF)

3. Q. Cai and L. Gao and J. Xue. Region-based partial dead code elimination on predicated code. In 2004 International Conference on Compiler Construction (CC'04) , pages 150 -- 166, Barcelona, Spain, 2004. (PDF)

4. B. Kurniawan and J. Xue. A comparative study of web application design models using the Java technologies. In 6th Asia Pacific Web Conference , pages 711 -- 721, Hangzhou, China, 2004.

5. P. Nguyen and J. Xue. Strength reduction for loop-invariant types. In 27th Australasian Computer Science Conference (ACSC'04) , pages 213 -- 222, Dunedin, New Zealand, 2004 (Best Student Paper). (PDF)

2003

1. X. Vera, B. Lisper and J. Xue. Data caches in multitasking hard real-time systems. In 24th IEEE International Real-Time Systems Symposium (RTSS'03), pages 154 -- 165, Cancun, Mexico, 2003. (PDF)

2. Q. Huang, J. Xue and X. Vera. Code tiling for improving the cache performance of PDE solvers. In 2003 International Conference on Parallel Processing (ICPP'03), pages 615 - 625, Kaohsiung, Taiwan, 2003. (PDF)

3. X. Vera, B. Lisper and J. Xue. Data cache locking for higher program predictability. In 2003 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'03), pages 272 - 282, San Diego, 2003. (PDF)

4. Q. Cai and J. Xue. Optimal and efficient speculation-based partial redundancy elimination. In 1st Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'03) , pages 91 -- 102, San Francisco, 2003. (PDF)

2002

1. X. Vera and J. Xue. Let's study whole-program cache behaviour analytically. In 8th International Symposium on High-Performance Computer Architecture (HPCA-8), pages 175 -- 186, Boston, MA, 2002 (PDF)

2. X. Vera and J. Xue. Efficient compile-time analysis of cache behaviour for programs with IF statements. In 5th International Conference on Algorithms and Architectures for Parallel Processing (ICA³PP'02) , pages 396-407, Beijing, 2002.

3. P. Lenders and J. Xue. A generic localization method for VLSI implementation of algorithms. In 4th International Conference on Massively Parallel Computng Systems (MPCS'02) , pages 38 -- 44, Ischia, Italy, 2002.

4. J. Xue and W. Cai. Time-minimal tiling when rise is larger than zero. Parallel Computing, 28(6):915--939, 2002. (PDF)

5. P. Lenders and J. Xue. Eigenvectors-based parallelisation of nested loops with affine dependences. Parallel Algorithms and Applications, 17(3):227--248, 2002. (PDF)

6. J. Xue and P. Lenders. Space-time equations for non-unimodular mappings. International Journal of Computer Mathematics, 79(5):555-572, 2002. (PDF)

2001

1. S. Chen and J. Xue. Communication overhead on distributed memory machines. Parallel and Distributed Computing Practice, 1(4):93--104, 2001.

2. J. Xue. On nonsingular loop transformations using SUIF's dependence abstraction. In 2nd International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'01), pages 331-336, Taiwan, 2001. (Postscript)

2000

1. J. Xue. Loop Tiling for Parallelism. Kluwer Academic Publishers, August 2000 (280 pages). ISBN: 0-7923-7933-0.

2. P. Tang and J. Xue. Generating efficient tiled code for distributed memory machines. Parallel Computing, 26(11):1369--1410, 2000. (Postscript)

3. J. Xue. Time-minimal and processor-time-minimal loop tiling. In 4th International Conference on Algorithms and Archiectures for Parallel Processing (ICA³PP'00) , pages 264-280, Hongkong, 2000.

4. S. Chen and J. Xue. Optimal tiling for loops with parallelogram iteration spaces. In 1st International Conference on Parallel and Distributed Applications and Technologies (PDCAT'00) , pages 117-124, Hongkong, 2000.

1999

1. S. Chen and J. Xue. Partitioning and Scheduling loops on NOWs. Journal of Computer Communications, 22(11):1017-1033, 1999.

2. S. Chen and J. Xue. Communication overhead on distributed memory machines. In 4th Australian Computer Architecture Conference (ACAC'99) , pages 227-238, New Zealand, 1999.

1998

1. J. Xue and C.-H. Huang. Reuse-driven tiling for improving data locality. International Journal of Parallel Programming, 26(6):671-696, 1998. (Postscript)

2. S. Chen and J. Xue. An approach to tiling imperfect loop nests directly. In 2nd International Conference on Parallel and Distributed Computing and Networks (PDCN'98) , pages 455-461, Brisbane, 1998.

3. S. Chen and J. Xue. Issues of tiling double loops on distributed memory machines. In 5th Australian Parallel and Real-Time Systems (PART'98) , pages 377-388, Adelaide, 1998.

4. P. Tang and J. Xue. Job size for internet parallel computing. In 2nd International Conference on Parallel and Distributed Computing and Networks (PDCN'98), pages 565-570, Brisbane, 1998.

5. S. Chen, J. Xue, Y. Zhang and J. Ma. An expert control system for gas furnace pressure. In 2nd IEEE International Conference on Intelligent Processing Systems (ICIPS'98), pages 233-237, Piscataway, NJ, USA, 1998.

1997

1. J. Xue. Communication-minimal tiling of uniform dependence loops. Journal of Parallel and Distributed Computing, 42(1):42-59, 1997. (Postscript)

2. J. Xue. On tiling as a loop transformation. Parallel Processing Letters, 7(4):409-424, 1997. (Postscript)

3. J. Xue. Unimodular transformations of non-perfectly nested loops. Parallel Computing, 22(12):1621-1645, 1997. (Postscript)

4. P. Lenders and J. Xue. Eigenvectors-based parallelisation of nested loops with affine dependences. In 3rd International Conference on Algorithms and Architectures for Parallel Processing (ICA³PP'97), pages 357-366, Melbourne, 1997.

5. J. Xue and C.-H. Huang. Reuse-driven tiling for data locality. In 10th Workshop on Languages and Compilers for Parallel Computing (LCPC'97) , Lecture Notes in Computer Science 1366, pages 16-33, Minneapolis, Minn., 1997. Springer-Verlag.

1996

1. J. Xue. Generalising the unimodular approach to restructure imperfectly nested loops. Parallel Processing Letters, 6(3):401-414, 1996 (Postscript)

2. J. Xue. Transformations of nested loops with non-convex iteration spaces. Parallel Computing, 22(3):339-368, 1996. (Postscript)

3. J. Xue. Communication-minimal tiling of uniform dependence loops. In 9th Workshop on Languages and Compilers for Parallel Computing (LCPC'96) , Lecture Notes in Computer Science 1239, pages 300-319, San Jose, 1996. Springer-Verlag.

4. J. Xue. Affine-by-statement transformations for imperfectly nested loops. In 10th International Parallel Processing Symposium (IPPS'96), pages 34-38, Hawaii, 1996. (IPPS + SPDP => IPPS since 1999)

5. J. Xue. On loop restructuring by converting imperfect to perfect loop nests. In 2nd International Conference on Algorithms and Architectures for Parallel Processing (ICA³PP), pages 421-429, Singapore, 1996.

6. J. Xue. On tiling as a loop transformation. In 1996 SPDP Workshop on Challenges in Compiling for Scalable Parallel Systems, New Orleans, 1996. IEEE Computer Society Press.

1995

1. J. Xue. Closed-form mapping conditions for the synthesis of linear processor arrays. J. VLSI Signal Processing, 10(2):181-199, 1995. (Postscript)

2. J. Xue. Constructing DO loops for non-convex iteration spaces in compiling for parallel machines. In The 9th International Parallel Processing Symposium (IPPS'95), pages 364-368, Santa Barbara, 1995. IEEE Computer Society Press. (IPPS + SPDP => IPPS since 1999)

3. J. Xue. Non-unimodular code generation for parallel machines. In 1st International Conference on Algorithms and Architectures for Parallel Processing (ICA³PP'95), pages 181-184, Brisbane, 1995.

4. J. Xue. Scanning non-convex iteration spaces. In 4th International Conference on Young Computer Scientists, pages 114-121, Beijing, 1995.

1994

1. J. Xue. Automating non-unimodular loop transformations for massive parallelism. Parallel Computing, 20(5):711-728, 1994. (Postscript)

2. J. Xue. The design of optimal linear processor arrays with closed-form conditions. In High Performance Computing'94: Challenges into the 21st Century, pages 246-253, Singapore, 1994.

3. J. Xue. Syspar: A software package for systolising and parallelising nested loop algorithms. In IEEE region 10's 9th Annual International Conference Frontiers of Computer Technology, pages 551-555, Singapore, 1994.

4. J. Xue and P. Lenders. Avoiding data link and computational conflicts in mapping algorithms to lower-dimensional processor arrays. In Lionel M. Ni, editor, 1994 International Conference on Parallel and Distributed Systems, pages 567-572, Taiwan, 1994. IEEE Computer Society Press.

5. C. Lengauer and J. Xue. Adapting a sequential algorithm for a systolic design. In G. M. Megson, editor, Transformational Approaches to Systolic Design, Parallel and Distributed Computing Series, Chapter 8, pages 179-204. Chapman & Hall, 1994.

1993

1. J. Xue. An algorithm to automate non-unimodular transformations of loop nests. In The 5th IEEE Symposium on Parallel and Distributed Processing (SPDP'93) , pages 512-519, Dallas, 1993. IEEE Computer Society Press. (IPPS + SPDP => IPPS since 1999) (PDF)

2. J. Xue. A new formulation of mapping conditions for the synthesis of linear systolic arrays. In L. Dadda and B. W. Wah, editors, International Conference on Application Specific Array Processors (ASAP'93), pages 297-308, Venice, 1993. IEEE Computer Society Press. (PDF)

1992

1. J. Xue and C. Lengauer. The synthesis of control signals for one-dimensional systolic arrays. Integration, The VLSI Journal, 14(1):1-32, Nov. 1992. (Postscript)

2. J. Xue. On the loading, recovery and access of stationary data in systolic arrays. In L. Bouge, M. Cosnard, Y. Robert, and D. Trystram, editors, Parallel Processing: CONPAR92-VAPP V, Lecture Notes in Computer Science 634, pages 259-264. Elsevier (North-Holland), Lyon, Sept. 1992.

1991

1. J. Xue. Specifying control signals for systolic arrays by uniform recurrence equations. Parallel Processing Letters, 1(2):83-93, 1991.

2. C. Lengauer and J. Xue. A systolic array for pyramidal algorithms. J. VLSI Signal Processing, 3(3):239-259, 1991.

3. J. Xue and C. Lengauer. On one-dimensional systolic arrays. In ACM International Workshop on Formal Methods in VLSI Design, Miami, 1991.

4. J. Xue and C. Lengauer. Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. In P. Quinton and Y. Robert, editors, Algorithms and Parallel VLSI Architectures II, pages 181-187. Elsevier (North-Holland), Toulouse, 1991.