Publications (Jingling Xue)

2018

  1. Feng Zhang and Jingling Xue. Poker: Permutation-based SIMD Execution of Intensive Tree Search by Path Encoding. In 15th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'18), pages ?? -- ??, Vienna, 2018.

  2. Qing Zhou, Lian Li, Lei Wang, Jingling Xue and Xiaobing Feng. May-Happen-in-Parallel Analysis with Static Vector Clocks. In 15th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'18), pages ?? -- ??, Vienna, 2018.

2017

  1. Jie Liu, Yue Li, Tian Tan and Jingling Xue. Reflection Analysis for Java: Uncovering More Reflective Targets Precisely. In 28th IEEE International Symposium on Software Reliability Engineering (ISSRE'17), pages ?? -- ??, Toulouse, France, 2017. (PDF (One of the Three Best Paper Award Nominees)

  2. Xuesong Su, Hui Wu, Jingling Xue. An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW Processors.In Special Issue of 2017 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'17), ACM Transactions on Embedded Computing Systems, 2017.

  3. Jieyuan Zhang, Yulei Sui and Jingling Xue. Incremental Analysis for Probabilistic Programs. In 24th International Static Analysis Symposium (SAS'17), pages 450 -- 472, New York, 2017.

  4. Tian Tan, Yue Li and Jingling Xue. Efficient and Precise Points-to Analysis: Modeling the Heap by Merging Equivalent Automata. In 2017 ACM Conference on Programming Language Design and Implementation (PLDI'17), pages 278 -- 291, 2017.

  5. Lian Li, Yi Lu and Jingling Xue. Dynamic Symbolic Execution for Polymorphism. In 2017 International Conference on Compiler Construction (CC'17), pages 120 -- 130, 2017.

  6. Yifei Zhang, Tian Tan, Yue Li and Jingling Xue. Ripple: Reflection Analysis for Android Apps in Incomplete Information Environments. In 7th ACM Conference on Data and Application Security and Privacy (CODASPY'17), pages 281 -- 288, Scottsdale, Arizona, 2017. (See also arXiv:1612.05343.)

  7. Xing Su, Xiangke Liao and Jingling Xue. Automatic Generation of Fast BLAS3-GEMM: A Portable Compiler Approach. In 14th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'17), pages 122 -- 133, Austin, 2017. (PDF) (One of the Four Best Paper Award Nominees)

  8. Y. Wang, T. Wang, D. Liu, Z. Shao and Jingling Xue. Fine Grained, Direct Access File System Support for Storage Class Memory. Journal of Systems Architecture, , 72:80--92, 2017.

2016

  1. Jianjun Xu, Xiankai Meng, Qingping Tan and Jingling Xue. Masking Soft Errors with Static Bitwise Analysis 23rd Asia-Pacific Software Engineering Conference (APSEC'16), Hamilton, New Zealand, pages 281 -- 288, 2016.

  2. Canqun Yang, Cheng Chen, Tao Tang, Xuhao Chen, Jianbin Fang and Jingling Xue. An Energy-Efficient Implementation of LU Factorization on Heterogeneous Systems. In 2016 International Conference on Parallel and Distributed Systems (ICPADS'16), Wuhan, China, pages 971 -- 979, 2016.

  3. Hua Yan, Yulei Sui, Shiping Chen, and Jingling Xue. Automated Memory Leak Fixing on Value-Flow Slices for C Programs. In 31st ACM/SIGAPP Symposium on Applied Computing (SAC'16) , Pisa, Pages 1386 -- 1393, 2016.

  4. Tian Tan, Yue Li and Jingling Xue. Making k-Object-Sensitive Pointer Analysis More Precise with Still k-Limiting. In 23nd International Static Analysis Symposium (SAS'16), pages 489 -- 510, Edinburgh, 2016. (PDF)

  5. Yulei Sui and Jingling Xue. On-Demand Strong Update Analysis via Value-Flow Refinement. In ACM SIGSOFT International Symposium on the Foundations of Software Engineering (FSE'16) , 2016.

  6. Duo Liu, Kan Zhong, Tianzheng Wang, Yi Wang, Zili Shao, Edwin H.-M. Sha, and Jingling Xue. Durable Address Translation in PCM-based Flash Storage Systems. IEEE Transactions on Parallel and Distributed Systems (TPDS), 2016.

  7. Feng Zhang, Peng Di, Hao Zhou, Xiangke Liao and Jingling Xue. RegTT: Accelerating Tree Traversals on GPUs by Exploiting Regularities. In 2016 International Conference on Parallel Processing (ICPP'16), pages 562 -- 571, Philadelphia, 2016. (PDF)

  8. Yulei Sui, Ding Ye, Yu Su and Jingling Xue. Eliminating Redundant Bounds Checks in Dynamic Buffer Overflow Detection Using Weakest Preconditions. IEEE Transactions on Reliability (TR), 65(4):1682--1699, 2016. (PDF)

  9. Yulei Sui, Xiaokang Fan, Hao Zhou and Jingling Xue. Loop-Oriented Array- and Field-Sensitive Pointer Analysis for Automatic SIMD Vectorization. In ACM SIGPLAN/SIGBED 2016 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'16), pages 41 -- 51, Santa Babara, 2016.

  10. Yue Li, Tian Tan, Yifei Zhang and Jingling Xue. Program Tailoring: Slicing by Sequential Criteria. In 30th European Conference on Object-Oriented Programming (ECOOP'16), pages 15:1 -- 15:27, Rome, 2016. (PDF) (Distinguished Paper Award)

  11. Yulei Sui and Jingling Xue. SVF: Interprocedural Static Value-Flow Analysis in LLVM. In 2016 International Conference on Compiler Construction (CC'16), pages 265 -- 266, 2016.

  12. Hao Zhou and Jingling Xue. A Compiler Approach for Exploiting Partial SIMD Parallelism. ACM Transactions on Architecture and Code Optimization (TACO), 13(1):11:1--11:26, 2016.

  13. Hao Zhou and Jingling Xue. Exploiting mixed SIMD parallelism by reducing data reorganization overhead. In 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'16), pages 59 -- 69, Barcelona, 2016. (Best Paper Award)

  14. Yulei Sui, Peng Di and Jingling Xue. Sparse Flow-Sensitive Pointer Analysis for Multithreaded C Programs. In 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'16), pages 160 -- 170, Barcelona, 2016.

  15. Hua Yan, Yulei Sui, Shiping Chen and Jingling Xue. Automated Memory Leak Fixing on Value-Flow Slices for C Programs. In 31st ACM/SIGAPP Symposium on Applied Computing (SAC'16), pages 1396 -- 1403, Pisa, 2016.

  16. Juan Chen, Yuhua Tang, Yong Dong, Jingling Xue, Zhiyuan Wang and Wenhao Zhou. Reducing Static Energy in Supercomputer Interconnection Networks Using Topology-Aware Partitioning. IEEE Transactions on Computers (TC), 65(8):2588--2602, 2016. (PDF)

2015

  1. Yu Su, Ding Ye, Jingling Xue and Xiangke Liao. An Efficient GPU Implementation of Inclusion-based Pointer Analysis. IEEE Transactions on Parallel and Distributed Systems (TPDS), 27(2):353-366, 2015.

  2. L. Wang, X. Liao, J. Xue, L. S. Wei, Y.C. Wen, X. Yang. Enhancement of Cooperation between File Systems and Applications on VFS Extensions for Optimized Performance. Science China Information Sciences, 58(9):1-10, 2015.

  3. Xiaokang Fan, Yulei Sui and Jingling Xue. Contention-Aware Scheduling for Asymmetric Multicore Processors. In 21st IEEE International Conference on Parallel and Distributed Systems, pages 742 -- 751, Melbourne, 2015.

  4. Jiacheng Zhao, Huimin Cui, Jingling Xue and Xiaobing Feng. Predicting Cross-Core Performance Interference on Multicore Processors with Regression Analysis. IEEE Transactions on Parallel and Distributed Systems (TPDS), 2015.

  5. Yi Wang, Tianzheng Wang, Zili Shao, Duo Liu and Jingling Xue. File System-Independent Block Device Support for Storage Class Memory. The International Workshop of Software-Defined Data Communications and Storage (SDDCS) 2015, in conjunction with IEEE INFOCOM 2015, Hongkong, 2015.

  6. Ryan Moore, Bruce Childers and Jingling Xue. Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors. In 12th IEEE International Conference on Embedded Software and Systems (ICESS'15), pages 957 -- 963, New York, 2015. (PDF)

  7. Yue Li, Tian Tan and Jingling Xue. Effective Soundness-Guided Reflection Analysis. In 22nd International Static Analysis Symposium (SAS'15), pages 162 -- 180, Saint-Malo, 2015. (PDF)

  8. Peng Di, Yulei Sui, Ding Ye and Jingling Xue. Region-Based May-Happen-in-Parallel Analysis for C Programs. In 2015 International Conference on Parallel Processing (ICPP'15), pages 889 -- 898, Beijing, 2015. (PDF)

  9. Feng Wang, Hao Jiang, Ke Zuo, Xing Su, Jingling Xue and Canqun Yang. Design and Implementation of a Highly Efficient DGEMM for 64-bit ARMv8 Multi-Core Processors. In 2015 International Conference on Parallel Processing (ICPP'15), pages 200 -- 209, Beijing, 2015. (PDF)

  10. Wenting He, Huimin Cui, Binbin Lu, Jiacheng Zhao, Shengmei Li, Gong Ruan, Jingling Xue, Xiaobing Feng, Wensen Yang and Youliang Yan. Hadoop+: Modeling and Evaluating the Heterogeneity for MapReduce Applications in Heterogeneous Clusters. In 25th International Conference on Supercomputing (ICS'15), pages 143 -- 153, Newport Beach, 2015. (PDF)

2014

  1. Ding Ye, Yu Su, Yulei Sui and Jingling Xue. WPBound: Enforcing Spatial Memory Safety Efficiently at Runtime with Weakest Preconditions. In 25th IEEE International Symposium on Software Reliability Engineering (ISSRE'14), pages 88 -- 99, Naples, Italy, 2014. (PDF)

  2. Sen Ye, Yulei Sui and Jingling Xue. Region-based Selective Flow-Sensitive Pointer Analysis. In 21th International Static Analysis Symposium (SAS'14), pages 319 -- 336, Munich, 2014. (PDF)

  3. L. Wang, J. Xue and X. Yang. Acyclic Orientation Graph Coloring for Software-Managed Memory Allocation. Science China Information Sciences, 57(9):1-18, 2014.

  4. Yue Li, Tian Tan, Yulei Sui and Jingling Xue. Self-Inferencing Reflection Resolution for Java. In 28th European Conference on Object-Oriented Programming (ECOOP'14), pages 27 -- 53, Uppsala, 2014. (PDF)

  5. Xiang-Ke Liao, Can-Qun Yung, Tao Tang, Huizhan Yi, Feng Wang, Qiang Wu and Jingling Xue. OpenMC: Towards Simplifying Programming for TianHe Supercomputers. Journal of Computer Science and Technology (JCST), 29(3):532-- 546, 2014. (PDF)

  6. Yu Su, Ding Ye and Jingling Xue. Parallel Pointer Analysis with CFL-Reachability. In 2014 International Conference on Parallel Processing (ICPP'14), pages 451 -- 460, Minnesota, 2014. (PDF)

  7. Huimin Cui, Gong Ruan, Jingling Xue, Rui Xie, Lei Wang and Xiaobing Feng. A Collaborative Divide-and-Conquer K-Means Clustering Algorithm for Processing Large Data. In 2014 ACM International Conference on Computing Frontiers (CF'14), pages 20:1 -- 20:10, 2014.

  8. Yulei Sui, Ding Ye and Jingling Xue. Detecting Memory Leaks Statically with Full-Sparse Value-Flow Analysis. IEEE Transactions on Software Engineering (TSE), 40(2):107 -- 122, 2014.

  9. Ding Ye, Yulei Sui and Jingling Xue. Accelerating Dynamic Detection of Uses of Undefined Variables with Static Value-Flow Analysis. In 11th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'14), pages 154 -- 164, Orlando, Florida, 2014.

  10. Xuemeng Zhang, Hui Wu, Haiyan Sun and Jingling Xue. Lifetime-Holes-Aware Register Allocation for Clustered VLIW Processors. In International Conference on Design, Automation and Test in Europe (DATE'14), pages 90:1 -- 90:4, Dresden, 2014.

  11. Yulei Sui, Sen Ye, Jingling Xue and Jie Zhang. Making Context-Sensitive Inclusion-based Pointer Analysis Practical for Compilers Using Parameterised Summarisation. Software -- Practice and Experience (SPE), 44(12):1485 -- 1510, 2014. (PDF)

2013

  1. Yu Su, Ding Ye and Jingling Xue. Accelerating Inclusion-based Pointer Analysis on Heterogeneous CPU-GPU Systems. In 2013 IEEE International Conference on High Performance Computing (HiPC'13) , pages 149 -- 158, 2013. (PDF)

  2. Jianli Li, Jingling Xue, Xinwei Xie, Qing Wan, Qingping Tan, Lanfang Tan. Epipe: a Low-Cost Fault-Tolerance Technique Considering WCET Constraints. Journal of Systems Architecture, 59(10-D):1383 -- 1393, 2013.

  3. Jiacheng Zhao, Huimin Cui, Jingling Xue, Xiaobing Feng, Youliang Yan and Wensen Yang. An Empirical Model for Predicting Cross-Core Performance Interference on Multicore Processors. In 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT'13) , pages 201 -- 212, Edinburgh, 2013. (PDF)

  4. Lin Gao, Lian Li, Jingling Xue and Pen-Chung Yew. SEED: A Statically-Greedy and Dynamically-Adaptive Approach for Speculative Loop Execution. IEEE Transactions on Computers (TC), 62(5):1004--1016, 2013. (PDF)

  5. Xinwei Xie, Jingling Xue and Jie Zhang. AccuLock: Accurate and Efficient Detection of Data Races. Software -- Practice and Experience (SPE), 43(5):543 -- 576, 2013. (PDF)

  6. Xuemeng Zhang, Hui Wu and Jingling Xue. Instruction scheduling with k-successor tree for clustered VLIW processors. Design Automation for Embedded Systems, 439 -- 458, 2013. (PDF)

  7. Yi Lu, Lei Shang, Xinwei Xie and Jingling Xue. An Incremental Points-to Analysis with CFL-Reachability. In 2013 International Conference on Compiler Construction (CC'13), pages 61 -- 81, Rome, Italy, 2013. (PDF)

  8. Yi Lu, John Potter and Jingling Xue. Structural Lock Correlation with Ownership Types. In 2013 European Symposium of Programming (ESOP'13), pages 391 -- 410, Rome, Italy, 2013. (PDF)

  9. Huimin Cui, Qing Yi, Jingling Xue and Xiaobing Feng. Layout-oblivious Compiler Optimization for Matrix Computations. The 8th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'13), Berlin, Germany, 2013. (PDF)

  10. Yulei Sui, Yue Li and Jingling Xue. Query-Directed Adaptive Heap Cloning For Optimizing Compilers. In 11th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'13), pages 1 -- 11, ShenZhen, China, 2013. (PDF)
    (Best Paper Award)

  11. Huimin Cui, Qing Yi, Jingling Xue and Xiaobing Feng. Layout-oblivious Compiler Optimization for Matrix Computations. ACM Transactions on Architecture and Code Optimization (TACO), 9(4):35:1 -- 35:20, 2013. (PDF)

  12. Qing Wan, Hui Wu and Jingling Xue. Scratchpad Memory Aware Task Scheduling with Minimum Number of Preemptions on a Single Processor. In 8th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), pages 741 -- 748. Yokohama, Japan, 2013. (PDF)

2012

  1. Huimin Cui, Jingling Xue, Lei Wang, Yang Yang, Xiaobing Feng and Dongrui Fan. Extendable Pattern-Oriented Optimization Directives. ACM Transactions on Architecture and Code Optimization (TACO), 9(3):14:1--14:37, 2012.

  2. Huimin Cui, Qing Yi, Jingling Xue and Xiaobing Feng. Layout-oblivious Compiler Optimization for Matrix Computations. In 21st International Conference on Parallel Architectures and Compilation Techniques (PACT'12) , pages 429 -- 430, Minneapolis, 2012.

  3. Qiang Wu, Canqun Yang, Feng Wang and Jingling Xue. A Fast Parallel Implementation of Molecular Dynamics With the Morse Potential on a Heterogeneous Petascale Supercomputer. In IEEE 26th International Parallel and Distributed Processing Symposium WorkshopsI (IPDPSW'12), Shanghai, pages 140 -- 149, 2012.

  4. Yian Zhu, Yue Li, Jingling Xue, Tian Tan, Jialong Shi, Yang Shen and Chunyan Ma. What is System Hang and How to Handle it. In 23rd IEEE International Symposium on Software Reliability Engineering (ISSRE'12), pages 141 -- 150, Dallas, TX, 2012. (PDF)

  5. Yi Lu, John Potter and Jingling Xue. Ownership Types for Object Synchronisation. In 10th Asian Symposium on Programming Languages and Systems (APLAS'12), pages 18 -- 33. Kyoto, Japan, 2012. (PDF)

  6. Peng Di, Ding Ye, Yu Su, Yulei Sui and Jingling Xue. Automatic Parallelization of Tiled Loop Nests with Enhanced Fine-Grained Parallelism on GPUs. In 2012 International Conference on Parallel Processing (ICPP'12), pages 350 -- 359, Pittsburgh, 2012. (PDF)

  7. Lei Shang, Yi Lu and Jingling Xue. Fast and Precise Points-to Analysis with Incremental CFL-Reachability Summarisation. In 27th IEEE/ACM International Conference on Automated Software Engineering (ASE'12), pages 270 -- 273, Essen, Germany, 2012. (PDF)

  8. Yulei Sui, Ding Ye and Jingling Xue. Static Memory Leak Detection Using Full-Sparse Value-Flow Analysis. In International Symposium on Software Testing and Analysis (ISSTA'12), pages 254 -- 264, Minneapolis, MN, 2012. (PDF)

  9. Qing Wan, Hui Wu and Jingling Xue. WCET-Aware Data Selection and Allocation for Scratchpad Memory. In ACM SIGPLAN/SIGBED 2012 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'12), pages 41 -- 50, Beijing, 2012. (PDF)

  10. Yang Yang, Huimin Cui, Xiao-Bing Feng and Jingling Xue. A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs. Journal of Computer Science and Technology (JCST), 27(1):57-- 74, 2012. (PDF)

  11. Peng Di, Hui Wu, Jingling Xue, Feng Wang and Canqun Yang. Parallelizing SOR for GPGPUs Using Alternate Loop Tiling. Parallel Computing, 37(6-7):310 -- 328, 2012. (PDF)

  12. Xinhai Xu, Xuejun Yang, Jingling Xue, Yufei Lin and Yisong Lin. PartialRC: A Partial Recomputing Method for Efficient Fault Recovery on GPGPUs. Journal of Computer Science and Technology (JCST), 27(2):240--255, 2012.

  13. Yi Lu, John Potter, Chenyi Zhang and Jingling Xue. A Type and Effect System for Determinism in Multithreaded Programs. In 2012 European Symposium of Programming (ESOP'12), pages 518 -- 538, Tallinn, Estonia, 2012. (PDF)

  14. Huimin Cui, Qing Yi, Jingling Xue, Lei Wang, Yang Yang and Xiaobing Feng. A highly-parallel reuse distance analysis algorithm on GPUs. In 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS'12)), pages 1080 -- 1092, Shanghai, China 2012. (PDF)

  15. Lei Shang, Xinwei Xie and Jingling Xue. On-Demand Dynamic Summary-Based Points-to Analysis. In 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'12), pages 264 -- 274, San Jose, California, 2012.

  16. Xuejun Yang, Li Wang and Jingling Xue. Comparability Graph Coloring for Optimizing Utilization of Software-Managed Stream Register Files for Stream Processors. ACM Transactions on Architecture and Code Optimization (TACO), 9(1):5:1 -- 5:30, 2012.

  17. L Wang, J. Xue and X. Yang. Optimizing Modulo Scheduling to Achieve Reuse and Concurrency for Stream Processors. Journal of Supercomputing, 59(3):1229-1251, 2012. (PDF)

  18. Xuejun Yang, Zhiyuan Wang, Jingling Xue and Yun Zhou. The Reliability Wall for Exascale Supercomputing. IEEE Transactions on Computers (TC), 61(6):767 -- 779, 2012. (PDF)

2011

  1. Yulei Sui, Sen Ye, Jingling Xue and Pen-Chung Yew. SPAS: Scalable Path-Sensitive Pointer Analysis on Full-Sparse SSA. In 9th Asian Symposium on Programming Languages and Systems (APLAS'11), pages 155 -- 171. Kenting, Taiwan, 2011. (PDF)

  2. Xuemeng Zhang, Hui Wu and Jingling Xue. An Efficient Heuristic for Instruction Scheduling on Clustered VLIW Processors. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'11), pages 35 -- 44, Taipei, 2011.

  3. Lian Li, Jingling Xue and Jens Knoop. Scratchpad Memory Allocation for Data Aggregates via Interval Coloring in Superperfect Graphs. ACM Transactions on Embedded Computing Systems (TECS), 10(2):28-1 -- 28:48, 2011.

  4. Duo Liu, Yi Wang, Zili Shao, Minyi Guo and Jingling Xue. Optimally Maximizing Iteration-Level Loop Parallelism. IEEE Transactions on Parallel and Distributed Systems (TPDS), 23(3):564 -- 572, 2011. (PDF)

  5. Yong Guan and Jingling Xue Leakage-Aware Modulo Scheduling for Embedded VLIW Processors. Journal of Computer Science and Technology (JCST), 26(3):405 -- 417, 2011.

  6. Peng Di and Jingling Xue. Model-Driven Tile Size Selection for DOACROSS Loops on GPUs. In 17th International European Conference on Parallel and Distributed Computing (Euro-Par'11),pages 401 -- 412, Bordeaux, France, 2011. (PDF)

  7. Sabbir Mahmud, Hui Wu and Jingling Xue. Efficient Energy Balancing Aware Multiple Base Station Deployment for WSNs. In 8th European Conference on Wireless Sensor Networks (EWSN'11), pages 179 -- 194, Bonn, Germany, 2011. (PDF)

  8. Xinwei Xie and Jingling Xue. AccuLock: Accurate and Efficient Detection of Data Races. In 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'11), pages 201 -- 212, Chamonix, France, 2011. (PDF)

  9. Huimin Cui, Jingling Xue, Lei Wang, Yang Yang, Xiaobing Feng and DongRui Fan. Extendable Pattern-Oriented Optimization Directives. In 9th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'11), pages 107 -- 118, Chamonix, France, 2011. (PDF)

  10. Huimin Cui, Lei Wang, Jingling Xue, Xiaobing Feng and Yang Yang. Automatic Library Generation for BLAS3 on GPUs. In 25th IEEE International Parallel and Distributed Processing Symposium (IPDPS'11)), pages 255 -- 265, Anchorage (Alaska), USA, 2011. (PDF)

  11. Meng Wang, Zili Shao and Jingling Xue. On Reducing Hidden Redundant Memory Accesses for DSP Applications. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 19(6):997--1010, 2011. (PDF)

2010

  1. Anderson Kuei-An Ku, Jingling Xue and Yong Guan. Gather/scatter hardware support for accelerating Fast Fourier Transform. Journal of Systems Architecture, 56(12):667-684, 2010.

  2. Xuejun Yang, Li Wang, Jingling Xue, Tao Tang, Xiaoguang Ren and Sen Ye. Improving Scratchpad Allocation with Demand-Driven Data Tiling. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'10), Scottsdale, AZ, 2010.

  3. Hui Wu, Jingling Xue, and Sridevan Parameswaran. Optimal WCET-Aware Code Selection for Scratchpad Memory. In 2010 International Conference on Embedded Software (EMSOFT'10), Scottsdale, AZ, 2010.

  4. Peng Di, Qing Wan, Xuemeng Zhang, Hui Wu and Jingling Xue. Toward Harnessing DOACROSS Parallelism for Multi-GPGPUs. In 2010 International Conference on Parallel Processing (ICPP'10), San Diego, 2010. (PDF)

  5. Xuejun Yang, Ying Zhang, Xicheng Lu, Jingling Xue, Ian Rogers, Gen Li and Xudong Fang. Exploiting the Reuse Supplied by Loop-Dependent Stream References for Stream Processors. ACM Transactions on Architecture and Code Optimization (TACO), 7(2):11:1 -- 11:35, 2010.

  6. Hongtao Yu, Jingling Xue, Wei Huo, Xiaobing Feng, Zhaoqing Zhang. Level by Level: Making Flow- and Context-Sensitive Pointer Analysis Scalable for Millions of Lines of Code. In 8th Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'10), pages 218 -- 229, Toronto, 2010.

  7. Li Wang, Jingling Xue and Xuejun Yang. Reuse-Aware Modulo Scheduling for Stream Processors. In International Conference on Design, Automation and Test in Europe (DATE'10) , Dresden, 2010. (PDF)

  8. Lin Gao, Jingling Xue and Tin-Fook Ngai. Loop Recreation for Thread-Level Speculation on Multicore Processors. Software -- Practice and Experience (SPE), 40(1):45 -- 72, 2010. (PDF)

  9. Wei Mi, Xiaobing Feng, Jingling Xue and Yao-Cang Jia. Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors. In 7th IFIP International Conference on Network and Parallel Computing (NPC'10) , pages 329-343, ZhengZhou, 2010. (PDF)

2009

  1. Wei Mi, Xiao-Bing Feng, Yao-Cang Jia, Li Chen and Jingling Xue. PARBLO: Page-Allocation-Based DRAM Row Buffer Locality Optimization. Journal of Computer Science and Technology (JCST), 24(6): 1086 -- 1097, 2009.

  2. Lian Li, Hui Feng and Jingling Xue. Compiler-directed scratchpad memory management via graph coloring. ACM Transactions on Architecture and Code Optimization (TACO), 6(3):9:1 -- 9:17, 2009.

  3. Yi Lu, John Potter and Jingling Xue. Ownership Downgrading for Ownership Types. In The Seventh Asian Symposium on Programming Languages and Systems (APLAS'09) , pages 144 -- 160, Seoul, 2009. (PDF)

  4. Peng Di, Jingling Xue, Changjun Hu and Jingjing Zhou. A Cache-Efficient Parallel Gauss-Seidel Solver with Alternating Tiling. In 2009 International Conference on Parallel and Distributed Systems (ICPADS'09), ShenZhen, China, pages 244 -- 251, 2009.

  5. Duo Liu, Zili Shao, Meng Wang, Minyi Guo and Jingling Xue. Optimal Loop Parallelization for Maximizing Iteration-Level Parallelism. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'09), pages 67 -- 76, Grenoble, France, 2009.

  6. Lin Gao, Lian Li, Jingling Xue and Tin-Fook. Ngai. Exploiting Speculative TLP in Recursive Programs by Dynamic Thread Prediction. In 2009 International Conference on Compiler Construction (CC'09), pages 78 -- 93, York, UK, 2009. (PDF)

  7. Xuejun Yang, Li Wang, Jingling Xue, Yu Deng and Ying Zhang. Comparability Graph Coloring for Optimizing Utilization of Stream Register Files in Stream Processors. In 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'09) , pages 111 -- 120, North Carolina, 2009. (PDF)

2008

  1. Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik. ACS: an Addressless Configuration Support for Partial Reconfigurations. In IEEE International Conference on Field-Programmable Technology (FPT08) , pages 161 -- 168, Taiwan, 2008. (PDF)

  2. Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li and Guibin Wang. Exploiting Loop-Dependent Stream Reuse for Stream Processors. In 17th International Conference on Parallel Architectures and Compilation Techniques (PACT'08) , pages 28 -- 37, Toronto, 2008.

  3. Lin Gao, Quan Hoang Nyugen, Lian Li, Jingling Xue and Tin-Fook Ngai. Thread-Sensitive Modulo Scheduling for Multicore Processors. In 2008 International Conference on Parallel Processing (ICPP'08), pages 132 -- 140, Portland, Oregon, 2008. (PDF)

  4. Anderson Kuei-An Ku, Jenny Yi-Chun Kuo and Jingling Xue. A Gather/Scatter Hardware Support for Efficient Fast Fourier Transform. In 13th Asia-Pacific Computer Systems Architecture Conference (ACSAC'08), pages 1 -- 8, Taiwan, 2008.

  5. Anderson Kuei-An Ku, Jenny Yi-Chun Kuo and Jingling Xue. Hardware Support for Efficient Sparse Matrix Vector Multiplication. In 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC-08) , pages 37 -- 43, Shanghai, 2008.

  6. L. Wang, X. Yang, J. Xue, Y. Deng, X. Yan, T. Tang and Q. H. Nguyen. Optimizing Scientific Application Loops on Stream Processors. In ACM SIGPLAN/SIGBED 2008 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), pages 161 -- 170, Tucson, AZ, 2008.

  7. P. Lenders and J. Xue. Factorization of Singular Integer Matrices. Linear Algebra and its Applications, 428(4): 1046-1055, 2008. (PDF)

  8. B. Scholz, B. Burgstaller and J. Xue. Minimal Placement of Bank Selection Instructions for Partitioned Memory Architectures. ACM Transactions on Embedded Computing Systems (TECS), 7(2):12:1 -- 12:32, 2008.

  9. J. Xue, M. Guo and D. Wei. Improving the Parallelism of Iterative Methods by Aggressive Loop Fusion. Journal of Supercomputing, 43(2):147-164, 2008. (PDF)

2007

  1. L. Gao, L. Li, J. Xue and T.K  Ngai. Loop Recreation for Thread-Level Speculation. In 2007 International Conference on Parallel and Distributed Systems (ICPADS'07), Hsingchu, Taiwan, 2007. (PDF)

  2. L. Li, H. Wu, H. Feng and J. Xue. Towards Data Tiling for Whole Programs in Scratchpad Memory Allocation. In 12th Asia-Pacific Computer Systems Architecture Conference (ACSAC'07), pages 63 -- 74, Seoul, Korea, 2007.

  3. L.  Pan, J. Xue, M. Lai, M. Dillencourt and L. Bic. Toward Automatic Data Distribution for Migrating Computations. In 2007 International Conference on Parallel Processing (ICPP'07), Xian, China, 2007. (PDF)

  4. Y. Lu, J. Potter and J. Xue. Validity Invariants and Effects. In 21st European Conference on Object-Oriented Programming (ECOOP'07), pages 202 -- 226, Berlin, 2007. (PDF)

  5. L. Li, Q. H. Nguyen and J. Xue. Scratchpad Allocation for Data Aggregates in Superperfect Graphs. In ACM SIGPLAN/SIGBED 2007 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), pages 207 -- 216, San Diego, 2007.

  6. X. Vera, B. Lisper and J. Xue. Data Cache Locking for Tight Timing Calculations. ACM Transactions on Embedded Computing Systems (TECS), 7(1):14:1 -- 14:38, 2007.

  7. J. Xue, P. Nguyen and J. Potter. Interprocedural Side-Effect Analysis for Incomplete Object-Oriented Software Modules. Journal of Systems and Software, 80(1):92-105, 2007.

  8. L. Li and J. Xue. Trace-based Leakage Energy Optimisations at Link Time. Journal of Systems Architecture, 53(1):1--20, 2007.

2006

  1. B. Scholz, B. Burgstaller and J. Xue. Minimizing Bank Selection Instructions for Partitioned Memory Architectures. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'06), pages 201 -- 211, Seoul, Korea, 2006. (PDF)
    (Best Paper Nomination)

  2. B.  Ye, M. Guo and J. Xue. CoopStream: A Cooperative Cache Based Streaming Schedule Scheme for On-demand Media Services on Overlay Networks. In 2006 International Conference on Parallel Processing (ICPP'06), pages 577 -- 584, Columbus, Ohio, USA, 2006. (PDF)

  3. H. Wu, J. Jaffar and J. Xue. Instruction Scheduling with Release Times and Deadlines on ILP Processors. In 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06), pages 51 -- 60, Sydney, Australia, 2006. (PDF)

  4. L. Li and J. Xue. Trace-based Data Cache Leakage Reduction at Link Time. In 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC'06), pages 175 -- 188, Shanghai, China, 2006.

  5. J. Xue and Q. Cai. A lifetime optimal algorithm for speculative PRE. ACM Transactions on Architecture and Code Optimization (TACO), 3(2):115-155, 2006.

  6. J. Xue, Q. Cai and L. Gao. Partial dead code elimination on predicated code regions. Software -- Practice and Experience (SPE), 36(15): 1655-1685, 2006.

  7. J. Xue and J. Knoop. A Fresh Look at PRE as a Maximum Flow Problem. In 2006 International Conference on Compiler Construction (CC'06), pages 139--154, Vienna, Austria, 2006. (PDF)

2005

  1. J. Xue and Q. Huang. Code Tiling: One Size Fits All. In G. T. Yang and M. Guo, editors, High Performance Computing: Paradigm and Infrastructure, Chapter 11, pages 219--240. John Wiley & Sons Inc., 2005.

  2. C. Yang, X. Yang and J. Xue. Improving the Performance of GCC by Exploiting IA-64 Architectural Features. In 10th Asia-Pacific Computer Systems Architecture Conference (ACSAC'05) , pages 236 -- 251, Singapore, 2005. (Postscript)

  3. J. Xue. Aggressive loop fusion for improving locality and parallelism of iterative methods. In 3rd International Symposium on Parallel and Distributed Processing and Applications (ISPA'05) , pages 224 -- 238, Nanjing, China, 2005. (Postscript)

  4. L.  Li, L. Gao and J. Xue. Memory coloring: a compiler approach for automatic scratchpad memory management. In 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05) , pages 329 -- 338, Saint Louis, Missouri, 2005. (PDF)

  5. J.  Xue, Q. Huang and M. Guo. Enabling loop fusion and tiling for cache performance by fixing fusion-preventing data dependences. In 2005 International Conference on Parallel Processing (ICPP'05), pages 107 - 115, Oslo, Norway, 2005. (PDF)

  6. J. Xue and P. Nguyen. Completeness analysis for incomplete object-oriented programs. In 2005 International Conference on Compiler Construction (CC'05), pages 271--286, Edinburgh, UK, 2005. (PDF)

  7. P. Nguyen and J. Xue. Interprocedural side-effect analysis for Java programs in the presence of dynamic class loading. In 28th Australasian Computer Science Conference (ACSC'05) , pages 9 -- 18, Newcastle, Australia, 2005. (PDF)
    (Best Paper Award)

2004

  1. J. Xue and X. Vera. Efficient and accurate analytical modeling of whole-program data cache behavior. IEEE Transactions on Computers, 53(5):547--566, 2004.

  2. L. Li and J. Xue. A trace-based binary compilation framework for energy-aware computing. In ACM SIGPLAN/SIGBED 2004 International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04) , pages 95 -- 106, Warshington, DC, 2004. (PDF)

  3. Q. Cai and L. Gao and J. Xue. Region-based partial dead code elimination on predicated code. In 2004 International Conference on Compiler Construction (CC'04) , pages 150 -- 166, Barcelona, Spain, 2004. (PDF)

  4. B. Kurniawan and J. Xue. A comparative study of web application design models using the Java technologies. In 6th Asia Pacific Web Conference , pages 711 -- 721, Hangzhou, China, 2004.

  5. P. Nguyen and J. Xue. Strength reduction for loop-invariant types. In 27th Australasian Computer Science Conference (ACSC'04) , pages 213 -- 222, Dunedin, New Zealand, 2004. (PDF)
    (Best Student Paper Award)

2003

  1. X. Vera, B. Lisper and J. Xue. Data caches in multitasking hard real-time systems. In 24th IEEE International Real-Time Systems Symposium (RTSS'03), pages 154 -- 165, Cancun, Mexico, 2003. (PDF)

  2. Q. Huang, J. Xue and X. Vera. Code tiling for improving the cache performance of PDE solvers. In 2003 International Conference on Parallel Processing (ICPP'03), pages 615 - 625, Kaohsiung, Taiwan, 2003. (PDF)

  3. X. Vera, B. Lisper and J. Xue. Data cache locking for higher program predictability. In 2003 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS'03), pages 272 - 282, San Diego, 2003.

  4. Q. Cai and J. Xue. Optimal and efficient speculation-based partial redundancy elimination. In 1st Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO'03) , pages 91 -- 102, San Francisco, 2003. (PDF)

2002

  1. X. Vera and J. Xue. Let's study whole-program cache behaviour analytically. In 8th International Symposium on High-Performance Computer Architecture (HPCA-8), pages 175 -- 186, Boston, MA, 2002 (PDF)

  2. X. Vera and J. Xue. Efficient compile-time analysis of cache behaviour for programs with IF statements. In 5th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP'02) , pages 396-407, Beijing, 2002.

  3. P. Lenders and J. Xue. A generic localization method for VLSI implementation of algorithms. In 4th International Conference on Massively Parallel Computng Systems (MPCS'02) , pages 38 -- 44, Ischia, Italy, 2002.

  4. J. Xue and W. Cai. Time-minimal tiling when rise is larger than zero. Parallel Computing, 28(6):915--939, 2002. (PDF)

  5. P. Lenders and J. Xue. Eigenvectors-based parallelisation of nested loops with affine dependences. Parallel Algorithms and Applications, 17(3):227--248, 2002. (PDF)

  6. J. Xue and P. Lenders. Space-time equations for non-unimodular mappings. International Journal of Computer Mathematics, 79(5):555-572, 2002. (PDF)

2001

  1. S. Chen and J. Xue. Communication overhead on distributed memory machines. Parallel and Distributed Computing Practice, 1(4):93--104, 2001.

  2. J. Xue. On nonsingular loop transformations using SUIF's dependence abstraction. In 2nd International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'01), pages 331-336, Taiwan, 2001. (Postscript)

2000

  1. J. Xue. Loop Tiling for Parallelism. Kluwer Academic Publishers, August 2000 (280 pages). ISBN: 0-7923-7933-0.

  2. P. Tang and J. Xue. Generating efficient tiled code for distributed memory machines. Parallel Computing, 26(11):1369--1410, 2000. (Postscript)

  3. J. Xue. Time-minimal and processor-time-minimal loop tiling. In 4th International Conference on Algorithms and Archiectures for Parallel Processing (ICA3PP'00) , pages 264-280, Hongkong, 2000.

  4. S. Chen and J. Xue. Optimal tiling for loops with parallelogram iteration spaces. In 1st International Conference on Parallel and Distributed Applications and Technologies (PDCAT'00) , pages 117-124, Hongkong, 2000.

1999

  1. S. Chen and J. Xue. Partitioning and Scheduling loops on NOWs. Journal of Computer Communications, 22(11):1017-1033, 1999.

  2. S. Chen and J. Xue. Communication overhead on distributed memory machines. In 4th Australian Computer Architecture Conference (ACAC'99) , pages 227-238, New Zealand, 1999.

1998

  1. J. Xue and C.-H. Huang. Reuse-driven tiling for improving data locality. International Journal of Parallel Programming, 26(6):671-696, 1998. (Postscript)

  2. S. Chen and J. Xue. An approach to tiling imperfect loop nests directly. In 2nd International Conference on Parallel and Distributed Computing and Networks (PDCN'98) , pages 455-461, Brisbane, 1998.

  3. S. Chen and J. Xue. Issues of tiling double loops on distributed memory machines. In 5th Australian Parallel and Real-Time Systems (PART'98) , pages 377-388, Adelaide, 1998.

  4. P. Tang and J. Xue. Job size for internet parallel computing. In 2nd International Conference on Parallel and Distributed Computing and Networks (PDCN'98), pages 565-570, Brisbane, 1998.

  5. S. Chen, J. Xue, Y. Zhang and J. Ma. An expert control system for gas furnace pressure. In 2nd IEEE International Conference on Intelligent Processing Systems (ICIPS'98), pages 233-237, Piscataway, NJ, USA, 1998.

1997

  1. J. Xue. Communication-minimal tiling of uniform dependence loops. Journal of Parallel and Distributed Computing, 42(1):42-59, 1997. (Postscript)

  2. J. Xue. On tiling as a loop transformation. Parallel Processing Letters, 7(4):409-424, 1997. (Postscript)

  3. J. Xue. Unimodular transformations of non-perfectly nested loops. Parallel Computing, 22(12):1621-1645, 1997. (Postscript)

  4. P. Lenders and J. Xue. Eigenvectors-based parallelisation of nested loops with affine dependences. In 3rd International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP'97), pages 357-366, Melbourne, 1997.

  5. J. Xue and C.-H. Huang. Reuse-driven tiling for data locality. In 10th Workshop on Languages and Compilers for Parallel Computing (LCPC'97) , Lecture Notes in Computer Science 1366, pages 16-33, Minneapolis, Minn., 1997. Springer-Verlag.

1996

  1. J. Xue. Generalising the unimodular approach to restructure imperfectly nested loops. Parallel Processing Letters, 6(3):401-414, 1996 (Postscript)

  2. J. Xue. Transformations of nested loops with non-convex iteration spaces. Parallel Computing, 22(3):339-368, 1996. (Postscript)

  3. J. Xue. Communication-minimal tiling of uniform dependence loops. In 9th Workshop on Languages and Compilers for Parallel Computing (LCPC'96) , Lecture Notes in Computer Science 1239, pages 300-319, San Jose, 1996. Springer-Verlag.

  4. J. Xue. Affine-by-statement transformations for imperfectly nested loops. In 10th International Parallel Processing Symposium (IPPS'96), pages 34-38, Hawaii, 1996. (IPPS + SPDP => IPPS since 1999)

  5. J. Xue. On loop restructuring by converting imperfect to perfect loop nests. In 2nd International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), pages 421-429, Singapore, 1996.

  6. J. Xue. On tiling as a loop transformation. In 1996 SPDP Workshop on Challenges in Compiling for Scalable Parallel Systems, New Orleans, 1996. IEEE Computer Society Press.

1995

  1. J. Xue. Closed-form mapping conditions for the synthesis of linear processor arrays. J. VLSI Signal Processing, 10(2):181-199, 1995. (Postscript)

  2. J. Xue. Constructing DO loops for non-convex iteration spaces in compiling for parallel machines. In The 9th International Parallel Processing Symposium (IPPS'95), pages 364-368, Santa Barbara, 1995. IEEE Computer Society Press. (IPPS + SPDP => IPPS since 1999)

  3. J. Xue. Non-unimodular code generation for parallel machines. In 1st International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP'95), pages 181-184, Brisbane, 1995.

  4. J. Xue. Scanning non-convex iteration spaces. In 4th International Conference on Young Computer Scientists, pages 114-121, Beijing, 1995.

1994

  1. J. Xue. Automating non-unimodular loop transformations for massive parallelism. Parallel Computing, 20(5):711-728, 1994. (Postscript)

  2. J. Xue. The design of optimal linear processor arrays with closed-form conditions. In High Performance Computing'94: Challenges into the 21st Century, pages 246-253, Singapore, 1994.

  3. J. Xue. Syspar: A software package for systolising and parallelising nested loop algorithms. In IEEE region 10's 9th Annual International Conference Frontiers of Computer Technology, pages 551-555, Singapore, 1994.

  4. J. Xue and P. Lenders. Avoiding data link and computational conflicts in mapping algorithms to lower-dimensional processor arrays. In Lionel M. Ni, editor, 1994 International Conference on Parallel and Distributed Systems, pages 567-572, Taiwan, 1994. IEEE Computer Society Press.

  5. C. Lengauer and J. Xue. Adapting a sequential algorithm for a systolic design. In G. M. Megson, editor, Transformational Approaches to Systolic Design, Parallel and Distributed Computing Series, Chapter 8, pages 179-204. Chapman & Hall, 1994.

1993

  1. J. Xue. An algorithm to automate non-unimodular transformations of loop nests. In The 5th IEEE Symposium on Parallel and Distributed Processing (SPDP'93) , pages 512-519, Dallas, 1993. IEEE Computer Society Press. (IPPS + SPDP => IPPS since 1999) (PDF)

  2. J. Xue. A new formulation of mapping conditions for the synthesis of linear systolic arrays. In L. Dadda and B. W. Wah, editors, International Conference on Application Specific Array Processors (ASAP'93), pages 297-308, Venice, 1993. IEEE Computer Society Press. (PDF)

1992

  1. J. Xue and C. Lengauer. The synthesis of control signals for one-dimensional systolic arrays. Integration, The VLSI Journal, 14(1):1-32, Nov. 1992. (Postscript)

  2. J. Xue. On the loading, recovery and access of stationary data in systolic arrays. In L. Bouge, M. Cosnard, Y. Robert, and D. Trystram, editors, Parallel Processing: CONPAR92-VAPP V, Lecture Notes in Computer Science 634, pages 259-264. Elsevier (North-Holland), Lyon, Sept. 1992.

1991

  1. J. Xue. Specifying control signals for systolic arrays by uniform recurrence equations. Parallel Processing Letters, 1(2):83-93, 1991.

  2. C. Lengauer and J. Xue. A systolic array for pyramidal algorithms. J. VLSI Signal Processing, 3(3):239-259, 1991.

  3. J. Xue and C. Lengauer. On one-dimensional systolic arrays. In ACM International Workshop on Formal Methods in VLSI Design, Miami, 1991.

  4. J. Xue and C. Lengauer. Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations. In P. Quinton and Y. Robert, editors, Algorithms and Parallel VLSI Architectures II, pages 181-187. Elsevier (North-Holland), Toulouse, 1991.