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Oliver F. Diessel

Senior Lecturer

School of Computer Science and Engineering

University of New South Wales

UNSW SYDNEY NSW 2052 AUSTRALIA

Office: K17-501B

Tel: +61 2 9385 7384

Fax: +61 2 9385 5995

Email: odiessel@cse.unsw.edu.au

Infopage: https://www.cse.unsw.edu.au/db/staff/staff_details.php?ID=odiessel

Research Interests        Students Teaching Administration Profession Publications Personal Home

Keywords

• Reconfigurable computing: applications, algorithms, circuits
• Reconfigurable systems: design flows, tools, run-time environments
• Reconfigurable architectures: models, devices

Research Goal

Reconfigurable computing is concerned with adapting a system's hardware and software architecture to dynamic changes in energy or resource availability and performance requirements. The main challenge is to find creative solutions to on-line design problems. Specific areas of interest include: the specification and automatic synthesis of optimised dynamic hardware configurations; run-time environments and support for dynamically reconfigurable systems; and optimising applications using reconfigurable technology.

Current Projects

• High-performance reconfigurable computing for desktop computers with Jürgen Teich and others
• Reconfigurable Global Navigation Satellite receiver with Andrew Dempster and others
• Dynamically mapping executable code to reconfigurable functional units with Lih Wen Koh

Past Projects

• Compile- and run-time techniques and methods for supporting inter- and intra-task communications in multitasked dynamically reconfigurable systems
• Conception and evaluation of an adaptive processor architecture for dynamically mapping executing code into reconfigurable ALU arrays
• Development of a reconfigurable implementations of “Optical Flow” algorithms
• Architectural approaches to reducing reconfiguration overheads in SRAM-based FPGAs
• New algorithmic approaches to boosting the performance of FPGA routing algorithms on high-stress circuits
• Compile- and run-time techniques for deploying reconfigurable circuits specified using a high-level language based on the Circal process algebra
• Operating systems support for multiuser reconfigurable computers
• Development environments for reconfigurable computing
• Applications for the SPACE.2 reconfigurable computer
• Heuristic algorithms for scheduling dynamic FPGA reconfigurations
• Fundamental algorithms for the reconfigurable mesh model of parallel computation

Students        Research Teaching Administration Profession Publications Personal Home

PhD Students

• Lih Wen Koh, Reconfigurable Processor (current)
• Shannon Koh, Generating the Communications Infrastructure for Module-based Dynamic Reconfiguration of FPGAs (completed 2008)
• Usama Malik, Configuration Encoding Techniques for Fast FPGA Reconfiguration (completed 2006)
• Keith So, Physical Mapping of Circuits to FPGAs (supervised 2002 – 2003)
• Grant Wigley, Operating Systems for Reconfigurable Computing (co-supervised 1999)

Masters Students

• Christian Freiberger, Reconfiguration Manager for the Erlangen Slot Machine, University of Erlangen (hosted and co-supervised 2006)
• Christian Menz, Implementation of Global Cellular Automata, University of Darmstadt (hosted and co-supervised 2005)
• Jeremie Detrey, A Static Compiler for Mapping XCircal to Virtex FPGAs, ENS Lyon (hosted and supervised 2003)

Project Students

• Victor Lai, Rapid Partial Reconfiguration of Virtex-4, 2008
• Tristan Blakers, Analysis of cross-market alerting systems, 2007
• Tristan Blakers, MarketDB: Artificial stock market data generator, 2006
• Kevin Wang, Fast FPGA reconfiguration, 2006
• Kevin Stepniewski, FPGA implementation of BLAST, 2006
• Marco Della Torre, Enhanced Configuration System for Virtex FPGAs, 2005
• Victor Pang, Real-Time Optical Flow Computation using FPGAs, 2005
• Syd Pleno, Computer forensic disk analysis, 2005
• YiQi Huang, Evolutionary approaches to controller design adaptation, 2005
• Cheung Kong Kwok, Modelling reconfigurable functional units in SimpleScalar, 2005
• Sherman Lo, Ray tracing in hardware, 2004
• Andrew Cutler, Albert Leung, USB reconfigurable computing board design, 2004
• Daniella Ceic, Reconfigurable robot controller, 2002
• Pratyush Chalasani, Video processing using FPGAs, 2002
• Lih Wen Koh, FPGA implementation of Morphological Gradient operator, 2002
• Thien Diep, A high-level language for Reconfigurable Computing, 2001
• Usama Malik, Interpreter for FPGA specifications given in Circal, 2001
• Keith So, Compiling arbitrary behaviour to FPGAs, 2001
• Micahel Gauci, Trevor Tassell, Belay Zelleke, Video data compression, 1999

Teaching        Research Students Administration Profession Publications Personal Home

Computer Architecture

• COMP4211 – Advanced Architectures and Algorithms, UNSW (2004 – 2006)
• COMP3211 – Computer Architecture, UNSW (2002 – 2006)

Digital Systems

· COMP3222 – Digital Circuits and Systems, UNSW (2008)

· COMP2021 – Digital Systems Structures, UNSW (2000 – 2004)

· FPGA Design Course, Ho Chi Minh City University of Technology (2003)

Computer Programming

· COMP1921 – Data Structures and Algorithms, UNSW (2008)

· XCMP1000 – Computing 1, UNSW Asia (2007)

· COMP1021 – Computing 1B, UNSW (2005)

Professional Issues & Ethics

· COMP4920 – Professional Issues and Ethics, UNSW (2001)

Administrative Activities        Research Students Teaching Profession Publications Personal Home

• Academic Advisor, CSE Co-Op Programs

Professional Activities        Research Students Teaching Administration Publications Personal Home

Editorial Board

• ACM Transactions on Reconfigurable Technology and Systems

Program Committee Member

• IEEE Symp on Field-Programmable Custom Computing Machines
• Intl Conf on Field-Programmable Logic and Applications
• IEEE Intl Conf on Field-Programmable Technologies
• Reconfigurable Architectures Workshop
• Asia-Pacific Computer Systems Architecture Conference

Reviewer

• UK Engineering and Physical Sciences Research Council
• Hong Kong Research Grants Council
• ACM Transactions on Embedded Computing Systems
• IEEE Transactions on VLSI Systems
• IEEE Transactions on Computers
• IEEE Transactions on Education
• IET Computers and Digital Techniques
• Journal of Parallel and Distributed Computing
• Journal of VLSI Signal Processing Systems
• EURASIP Journal on Embedded Systems
• Integration, the VLSI Journal
• Institute of Electronics, Information and Communication Engineers
• Journal of Computer Science and Technology
• McGraw–Hill
• Oxford University Press

External Examiner

• University of Queensland
• Nanyang Technological University
• University of South Australia

Publications        Research Students Teaching Administration Profession Personal Home

Edited Books

[1] O. Diessel and J. A. Williams, editors. 2004 IEEE International Conference on Field-Programmable Technology (FPT’04). IEEE Computer Society Press, 2004.

Journal Publications

[2] B. Scheuermann, K. So, M. Guntsch, M. Middendorf, O. Diessel, H. ElGindy, and H. Schmeck. FPGA implementation of population-based ant colony optimization. Applied Soft Computing, Special Issue on Hardware Implementation of Soft Computing Techniques, 4(3): 303 – 322, August 2004.

[3] O. Diessel and H. ElGindy. On dynamic task scheduling for FPGA–based systems. International Journal of Foundations of Computer Science, Special Issue on Scheduling:  Theory and Applications, 12(5): 645 – 669, October 2001.

[4] O. Diessel and G. Milne. A hardware compiler realizing concurrent processes in reconfigurable logic. IEE Proceedings — Computers and Digital Techniques, 148(4): 152 – 162, September 2001.

[5] O. Diessel, H. ElGindy, M. Middendorf, H. Schmeck, and B. Schmidt. Dynamic scheduling of tasks on partially reconfigurable FPGAs. IEE Proceedings — Computers and Digital Techniques, Special Issue on Reconfigurable Systems, 147(3): 181 – 188, May 2000.

[6] B. Beresford-Smith, O. Diessel, and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes. Journal of Parallel and Distributed Computing, 39(1): 74 – 78, November 1996.

Conference Papers

[7] S. Koh and O. Diessel. The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’08), pages 65 – 76, 2008.

[8] U. Malik, O. Diessel and A. Dempster. Fast Code-Phase Alignment of GPS Signals using Virtex-4 FPGAs. In International Global Navigation Satellite Systems (IGNSS), 2007.

[9] S. Koh and O. Diessel, Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. In International Conference on Field Programmable Logic and Applications (FPL’07), pages 293 – 298, 2007.

[10] S. Koh and O. Diessel. Communications Infrastructure Generation for Modular FPGA Reconfiguration. In IEEE International Conference on Field-Programmable Technology (FPT2006), pages 321 – 324, 2006.

[11] L.W. Koh and O. Diessel. Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. In Asia-Pacific Computer Systems Architecture Conference (ACSAC), pages 161 – 174, 2006.

[12] U. Malik and O. Diessel. The Entropy of FPGA Reconfiguration. In International Conference on Field Programmable Logic and Applications (FPL’06), pages 261 – 266, 2006.

[13] S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs (Extended Abstract). In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’06), pages 273 – 274, 2006.

[14] S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. In International Conference on Architecture of Computing Systems, Workshops Proceedings, pages 173 – 182, 2006.

[15] M. Della Torre, U. Malik and O. Diessel. A configuration system architecture supporting bit-stream compression for FPGAs. In Asia-Pacific Computer Systems Architecture Conference, pages 415 – 428, 2005.

[16] U. Malik and O. Diessel. A Configuration memory architecture for fast run-time reconfiguration of FPGAs. In International Conference on Field-Programmable Logic and Applications. Pages 636 – 639, 2005.

[17] U. Malik and O. Diessel. On the placement and granularity of FPGA configurations. In IEEE International Conference on Field-Programmable Technology (FPT’04), pages 161 – 168, 2004.

[18] M. Guntsch, M. Middendorf, B. Scheuermann, O. Diessel, H. ElGindy, H. Schmeck, and K. So. Population based ant colony optimization on FPGA. In IEEE International Conference on Field-Programmable Technology (FPT’02), pages 125 – 132, 2002.

[19] U. Malik, K. So, and O. Diessel. Resource-aware run-time elaboration of behavioural FPGA specifications. In IEEE International Conference on Field-Programmable Technology (FPT’02), pages 68 – 75, 2002.

[20] O. Diessel, U. Malik, and K. So. Towards high-level specification, synthesis, and virtualization of programmable logic designs. In International Euro-Par Conference, pages 314 – 317, 2002.

[21] O. Diessel and U. Malik. An FPGA interpreter with virtual hardware management. In Reconfigurable Architectures Workshop, IPDPS 2002 Abstracts, page 155, 2002.

[22] G. Brebner and O. Diessel. Chip-based reconfigurable task management. In International Conference on Field-Programmable Logic and Applications, (FPL 2001), pages 182 – 191, 2001.

[23] O. Diessel and G. Milne. Behavioural language compilation with virtual hardware management. In, International Workshop on Field–Programmable Logic and Applications, pages 707 – 717, 2000.

[24] O. Diessel and G. Milne. Compiling process algebraic descriptions into reconfigurable logic. In Reconfigurable Architectures Workshop, IPDPS 2000, pages 916 – 923, 2000.

[25] O. Diessel, D. Kearney, and G. Wigley. A web–based multiuser operating system for reconfigurable computing. In Reconfigurable Architectures Workshop, IPPS/SPDP’99, pages 579 – 587, 1999.

[26] O. Diessel and H. ElGindy. On scheduling dynamic FPGA reconfigurations. In Australasian Conference on Parallel and Real–Time Systems (PART’98), pages 191 – 200, 1998.

[27] O. Diessel and H. ElGindy. Partial rearrangements of space–shared FPGAs (Extended abstract). In Reconfigurable Architectures Workshop, IPPS/SPDP’98, pages 913 – 918, 1998.

[28] O. Diessel and H. ElGindy. Partial FPGA rearrangement by local repacking. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 259, 1998.

[29] O. Diessel and H. ElGindy. Run–time compaction of FPGA designs. In International Workshop on Field–Programmable Logic and Applications, FPL’97, pages 131 – 140, 1997.

[30] O. Diessel, H. ElGindy, and B. Beresford-Smith. Partial task compaction reduces queuing delays in partitionable–array machines. In Australasian Conference on Parallel and Real–Time Systems, pages 186 – 194, 1996.

[31] O. Diessel, H. ElGindy, and L. Wetherall. Efficient broadcasting procedures for constrained reconfigurable meshes. In Australasian Conference on Parallel and Real–Time Systems, pages 85 – 88, 1996.

[32] B. Beresford-Smith, O. Diessel, and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes. In Australasian Computer Science Conference, pages 32 – 41, 1995.

[33] B. Beresford-Smith, O. Diessel, and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes (Extended abstract). In Australian Transputer and Occam User Group Conference, pages 28 – 39, 1994.

[34] H. B. Penfold, O. F. Diessel, and M. W. Bentink. A genetic breeding algorithm which exhibits self–organizing in neural networks. In International Symposium on A.I. Applications and Neural Networks, pages 293 – 296, 1990.

Technical Reports

[35] S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. Technical report TR0603, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, February 2006.

[36] U.Malik and O.Diessel. A Configuration Memory Architecture for Fast FPGA Reconfiguration. Technical report TR0509, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, April 2005.

[37] J. Detrey and O. Diessel. A constructive proof of the Turing completeness of Circal. Technical report TR0214, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, September 2002.

[38] J. Detrey and O. Diessel. SCCircal:  A static compiler mapping XCircal to Virtex FPGAs. Technical report TR0213, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, August 2002.

[39] O. Diessel and G. Milne. HCircal:  A hardware compiler for Circal. Technical report ACRC–00–013, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Mawson Lakes, SA, Mar.  2000.

[40] O. Diessel and G. Wigley. Opportunities for operating systems research in reconfigurable computing. Technical report ACRC–99–018, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Mawson Lakes, SA, Oct.  1999.

[41] O. Diessel. On Scheduling Dynamic FPGA Reconfigurations — A Partial Rearrangement Approach. Ph.D. thesis, Department of Computer Science and Software Engineering, The University of Newcastle, Callaghan, Australia, Jan.  1998.

[42] O. Diessel and H. ElGindy. Partial FPGA rearrangement by local repacking. Technical report 97–08, Department of Computer Science and Software Engineering, The University of Newcastle, Sept.  1997.

[43] O. Diessel and H. ElGindy. Ordered partial task compaction on mesh connected computers. Technical report 96–11, Department of Computer Science and Software Engineering, The University of Newcastle, Sept.  1996.

[44] O. Diessel. An investigation into the performance of a genetic algorithm for the selection of neural networks. B.E. project report, Department of Electrical Engineering and Computer Science, The University of Newcastle, Nov.  1990.

Invited Talks

[45] O. Diessel. Moving Run-Time Reconfiguration into the Mainstream, Microelectonics Embedded Systems Workshop, Singapore 2007

[46] O. Diessel. Reconfigurable Computing, Infocomm Development Authority of Singapore, 2006

[47] O. Diessel and S. Koh. Enabling RTR for Industry, Dagstuhl Seminar on Dynamically Reconfigurable Architectures, Germany 2006

[48] O. Diessel. Towards High-Level Specification & Synthesis of Dynamic Process Logic, Dynamic Straming Architectures Workshop, Caltech; Xilinx Research Labs; and University of Southern California, USA 2003

[49] O. Diessel. Operating Systems Support for Dynamically Reconfigurable Architectures, Dagstuhl Seminar on Reconfigurable Architectures, Germany 2000

Workshops

[50] O. Diessel, F. Engel, T. Percival, and N. Temperley. Reconfigurable Computing Workshop, National ICT Australia, 2005

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