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Oliver Diessel

 

Associate Professor

School of Computer Science and Engineering

University of New South Wales

UNSW SYDNEY NSW 2052 AUSTRALIA

 

Office: K17-501B

Tel: +61 2 9385 7384

Fax: +61 2 9385 5995

 

Email: o.diessel@unsw.edu.au

 

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Oliver's UNSW Research Infopage

 

Keywords

 

 

Research Goals

 

Reconfigurable computing is concerned with adapting a system's hardware and software to cope with run-time changes in functional requirements, performance targets, resource availability, and component failure. The main challenge is to find solutions to on-line design problems. Specific areas of interest include: the specification and automatic synthesis of optimal hardware configurations; run-time environments for dynamically reconfigurable systems; and optimising applications using reconfigurable technology.

 

Reconfigurable Systems Group Collaborators

 

 

Ongoing Projects

 

 

Past Projects

 

 

 

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Project Openings for Prospective Research Students

 

 

 

Requirements

o   Self-motivated

o   Knowledge of FPGA design, e.g., VHDL/Verilog, FPGA tools, High Level Synthesis desirable

o   Knowledge of C/C++, TCL, Python desirable

o   Good GPA – to obtain a scholarship at UNSW, the final two years of your undergraduate GPA must be at least 85% from a good school (ranked in top 200)

o   Good spoken and written English – see http://www.unsw.edu.au/english-requirements-policy

o   Previous research experience desirable – especially important to gain a UNSW scholarship

 

Training Outcomes

o   Research, writing and critical thinking skills

o   Good understanding of FPGA design

o   Good understanding of CAD tool development

 

Related Links

o   UNSW Scholarships

http://research.unsw.edu.au/postgraduate-research-scholarships

o   FPGA Career Opportunities in Australia

http://www.seek.com.au/JobSearch?SearchFrom=quickupper&SearchType=search+again&Keywords=FPGA&nation=3000

o   FPGA Career Opportunities in the US

http://www.glassdoor.com/Job/us-fpga-jobs-SRCH_IL.0,2_IN1_KO3,7.htm

 

Please email me to discuss these opportunities further.

 

 

PhD Students

 

 

Masters Students

 

 

Visiting Students

 

 

Project Students

 

Consult the CSE Thesis Topics database for suggested topics or email me to discuss your interests.

 

 

 

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Configurable Systems

 

 

Computer Architecture

 

 

Digital Systems

 

 

Computer Programming

 

 

Professional Issues & Ethics

 


 

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Professional Activities        Research    Students    Teaching    Administration    Publications    Personal    Home   

 

Editorial Board Member

 

 

Recent Organizing Roles

 

 

Program Committee Member

 

Publications        Research    Students    Teaching    Administration    Profession    Personal    Home   

 

Book

 

[1]         L. Gong and O. Diessel. Functional Verification of Dynamically Reconfigurable FPGA-based Systems. Springer, 2015.

 

Book Chapter

 

[2]         E. Cetin, O. Diessel, T. Li, J. A. Ambrose, T. Fisk, S. Parameswaran and A. G. Dempster. Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-based Heterogeneous Systems. In FPGAs and Parallel Architectures for Aerospace Applications, F. Kastensmidt and P. Rech (Eds), Springer, 2016.

 

Journal Publications

 

[3]         N.T.H. Nguyen, E. Cetin and O. Diessel. Scheduling Configuration Error Checks to Improve the Reliability of FPGA-based Systems. IET Computers & Digital Techniques, 13(3): 154 – 165, May 2019.

[4]         A. Kroh and O.Diessel. Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform. ACM Transactions on Reconfigurable Technology and Systems, 11(4), 25:1 – 25:22, January 2019.

[5]         D. Agiakatsikas, E. Cetin and O. Diessel. FMER: An Energy-Efficient Error Recovery Methodology for SRAM-based FPGA DesignsIEEE Transactions on Aerospace and Electronic Systems, 54(6): 2695 – 2712, December 2018.

[6]         N.T.H. Nguyen, D. Agiakatsikas, Z. Zhao, T. Wu, E. Cetin, O. Diessel and L. Gong. Reconfiguration Control Networks for FPGA-based TMR systems with modular error recoveryMicroprocessors and Microsystems 60: 86-95, July 2018.

[7]         Z. Zhao, N.T.H. Nguyen, D. Agiakatsikas, G. Lee, E. Cetin and O. Diessel, Fine-grained Module-based Error Recovery in FPGA-based TMR Systems. ACM Transactions on Reconfigurable Technology and Systems, 11(1), 4:1 – 4:23, March 2018.

[8]         G. Lee, E. Cetin and O. Diessel. Fault Recovery Time Analysis for Coarse-Grained Reconfigurable Architectures. ACM Transactions on Embedded Computing Systems, 17(2), 42:1 – 42:21, April 2018.

[9]         C. Wang, X. Li, Y. Chen, Y. Zhang, O. Diessel and X. Zhou. Service-oriented Architecture on FPGA-based MPSoC. IEEE Transactions on Parallel and Distributed Systems, 28(10): 2993 – 3006, October 2017.

[10]      P.H.W. Leong, H. Amano, J. Anderson, K. Bertels, J.M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, JK Lee, W. Luk, P. Lysaght, M. Platzner, V.K. Prasanna, T. Rissa, C. Silvano, H. So and Y. Wang. The First 25 Years of the FPL Conference – Significant Papers. ACM Transactions on Reconfigurable Technology and Systems, 10(2), 15:1 – 15:17, April 2017.

[11]      L. Gong and O. Diessel. Simulation-based Functional Verification of Dynamically Reconfigurable Systems. ACM Transactions on Embedded Computing Systems, 13(4), 97:1 – 97:23, February 2014.

[12]      S. Koh and O. Diessel. Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration. ACM Transactions on Reconfigurable Technology and Systems, 3(1), 4:1 – 4:36, January 2010.

[13]      B. Scheuermann, K. So, M. Guntsch, M. Middendorf, O. Diessel, H. ElGindy and H. Schmeck. FPGA implementation of population-based ant colony optimization. Applied Soft Computing, Special Issue on Hardware Implementation of Soft Computing Techniques, 4(3): 303 – 322, August 2004.

[14]      O. Diessel and H. ElGindy. On dynamic task scheduling for FPGA–based systems. International Journal of Foundations of Computer Science, Special Issue on Scheduling:  Theory and Applications, 12(5): 645 – 669, October 2001.

[15]      O. Diessel and G. Milne. A hardware compiler realizing concurrent processes in reconfigurable logic. IEE Proceedings — Computers and Digital Techniques, 148(4): 152 – 162, September 2001.

[16]      O. Diessel, H. ElGindy, M. Middendorf, H. Schmeck and B. Schmidt. Dynamic scheduling of tasks on partially reconfigurable FPGAs. IEE Proceedings — Computers and Digital Techniques, Special Issue on Reconfigurable Systems, 147(3): 181 – 188, May 2000.

[17]      B. Beresford-Smith, O. Diessel and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes. Journal of Parallel and Distributed Computing, 39(1): 74 – 78, November 1996.

 

Conference Papers

 

[18]      J. Fan and O. Diessel, On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’22).

[19]      T. Wu and O. Diessel, Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’22).

[20]      A. Kroh and O. Diessel. A Short-transfer Model for Tightly-coupled CPU-FPGA Platforms. In 2018 International Conference on Field-Programmable Technology (FPT’18).

[21]      D. Agiakatsikas, G. Lee, T. Mitchell, E. Cetin and O. Diessel. From C to Fault-Tolerant FPGA-based Systems. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’18).

[22]      N.T.H. Nguyen, E. Cetin and O. Diessel. Scheduling Voter Checks to Detect Configuration Memory Errors in FPGA-based TMR Systems. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’17), pages 1 – 4.

[23]      L. Gong, A. Kroh, D. Agiakatsikas, N.T.H. Nguyen, E. Cetin and O. Diessel. Reliable SEU Monitoring and Recovery using a Programmable Configuration Controller. In International Conference on Field-Programmable Logic and Applications (FPL’17), pages 1 – 6.

[24]      G. Lee, D. Agiakatsikas, T. Wu, E. Cetin and O. Diessel. TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’17), pages 129 – 132.

[25]      N.T.H. Nguyen, E. Cetin and O. Diessel. Scheduling Considerations for Voter Checking in TMR-MER Systems. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’17) page 30.

[26]      L. Gong, T. Wu, N.T.H.  Nguyen, D. Agiakatsikas, Z. Zhao, E. Cetin and O. Diessel. A Programmable Configuration Controller for Fault-Tolerant Applications. In 2016 International Conference on Field-Programmable Technology (FPT’16), pages 117124.

[27]      N.T.H. Nguyen, E. Cetin and O.Diessel. Dynamic Scheduling of Voter Checks in FPGA-based TMR Systems. In 2016 International Conference on Field-Programmable Technology (FPT’16), pages 169172.

[28]      Z. Zhao, D. Agiakatsikas, N.T.H. Nguyen, E. Cetin and O. Diessel. Fine-grained Module-based Error Recovery in FPGA-based TMR Systems. In 2016 International Conference on Field-Programmable Technology (FPT’16), pages 101108.

[29]      D. Agiakatsikas, E. Cetin and O. Diessel. FMER: A Hybrid Configuration Memory Error Recovery Scheme for Highly Reliable FPGA SoCs. In 26th International Conference on Field-Programmable Logic and Applications (FPL’16), 2016.

[30]      D. Agiakatsikas, N.T.H. Nguyen, Z. Zhao, T. Wu, E. Cetin, O. Diessel and L. Gong. Reconfiguration Control Networks for TMR Systems with Module-based Recovery. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’16), pages 88 – 91, 2016.

[31]      A. Kroh and O. Diessel. Towards OS kernel acceleration in heterogeneous systems. In First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC’15), 2015.

[32]      P.H.W. Leong, H. Amano, J. Anderson, K. Bertels, J.M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, JK Lee, W. Luk, P. Lysaght, M. Platzner, V.K. Prasanna, T. Rissa, C. Silvano, H. So and Y. Wang. Significant Papers from the First 25 Years of the FPL Conference. In 25th International Conference on Field-Programmable Logic and Applications (FPL’15).

[33]      V. T. Tran, N. C. Shivaramaiah, O. Diessel and A. G. Dempster. A programmable multi-GNSS baseband receiver. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1178 – 1181, 2015.

[34]      E. Cetin, O. Diessel and L. Gong. Improving Fmax of FPGA Circuits Employing DPR to Recover from Configuration Memory Upsets. In 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1190 – 1193, 2015.

[35]      E. Cetin, O. Diessel, T. Li, J. A. Ambrose, T. Fisk, S. Parameswaran and A. G. Dempster. Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-based Heterogeneous Systems. In First International Workshop on FPGAs for Aerospace Applications (FASA 2014).

[36]      E. Cetin, O. Diessel, L. Gong and V. Lai. Reconfiguration Network Design for SEU Recovery in FPGAs. In 2014 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1524 – 1527, 2014.

[37]      E. Cetin, O. Diessel, L. Gong and V. Lai. Towards Bounded Error Recovery Time in FPGA-based TMR Circuits Using Dynamic Partial Reconfiguration. In 23rd International Conference on Field-Programmable Logic and Applications (FPL), 2013.

[38]      L. Gong, O. Diessel, J. Paul and W. Stechele. RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study. In Parallel and Distributed Processing, International Symposium on, Reconfigurable Architecture Workshop (RAW), pages 106 – 113, 2013.

[39]      E. Cetin and O. Diessel. Guaranteed Fault Recovery Time for FPGA-based TMR Circuits Employing Partial Reconfiguration. In 2012 DAC Workshop 2nd International Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-oriented Environments (CHA’N’GE), 2012.

[40]      L. Gong and O. Diessel. Functionally Verifying State Saving & Restoration in Dynamically Reconfigurable Systems. In 2012 ACM/SIGDA International Symposium on FPGAs (FPGA’12), pages 241 – 244, 2012.

[41]      L. Gong and O. Diessel. ReSim: A Reusable Library for RTL Simulation of Dynamic Partial Reconfiguration. In 2011 International Conference on Field-Programmable Technology (FPT’11), pages 1 – 8, 2011.

[42]      B. Hredzak and O. Diessel. Optimization of Placement of Dynamic Network-on-chip Cores Using Simulated Annealing. In 37th Annual Conference of the IEEE Industrial Electronics Society (IECON 2011), pages 2400 – 2405, 2011.

[43]      L. Gong and O. Diessel. Modelling Dynamically Reconfigurable Systems for Simulation-based Functional Verification. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’11), pages 9 – 16, 2011.

[44]      B. Kwek, F. Sunarso, M. Teoh, A. van Zal, P. Preston and O. Diessel. FPGA-Based Video Processing for a Vision Prosthesis. In 2010 International Conference on Field-Programmable Technology (FPT’10), pages 345 – 348, 2010.

[45]      V. Lai and O. Diessel. ICAP-I: A Reusable Interface for the Internal Reconfiguration of Xilinx FPGAs. In 2009 International Conference on Field-Programmable Technology (FPT’09), pages 357 – 360, 2009.

[46]      J.Y.-C. Kuo, A.K-A. Ku, J. Xue, O. Diessel and U. Malik. ACS: An Addressless Configuration Support for Efficient Partial Reconfigurations. In 2008 International Conference on Field-Programmable Technology (FPT2008), pages 161 – 168, 2008.

[47]      S. Koh and O. Diessel. The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’08), pages 65 – 76, 2008.

[48]      U. Malik, O. Diessel and A. Dempster. Fast Code-Phase Alignment of GPS Signals using Virtex-4 FPGAs. In International Global Navigation Satellite Systems (IGNSS), 2007.

[49]      S. Koh and O. Diessel. Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. In International Conference on Field Programmable Logic and Applications (FPL’07), pages 293 – 298, 2007.

[50]      S. Koh and O. Diessel. Communications Infrastructure Generation for Modular FPGA Reconfiguration. In IEEE International Conference on Field-Programmable Technology (FPT2006), pages 321 – 324, 2006.

[51]      L.W. Koh and O. Diessel. Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. In Asia-Pacific Computer Systems Architecture Conference (ACSAC), pages 161 – 174, 2006.

[52]      U. Malik and O. Diessel. The Entropy of FPGA Reconfiguration. In International Conference on Field Programmable Logic and Applications (FPL’06), pages 261 – 266, 2006.

[53]      S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs (Extended Abstract). In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’06), pages 273 – 274, 2006.

[54]      S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. In International Conference on Architecture of Computing Systems, Workshops Proceedings, pages 173 – 182, 2006.

[55]      M. Della Torre, U. Malik and O. Diessel. A configuration system architecture supporting bit-stream compression for FPGAs. In Asia-Pacific Computer Systems Architecture Conference, pages 415 – 428, 2005.

[56]      U. Malik and O. Diessel. A Configuration memory architecture for fast run-time reconfiguration of FPGAs. In International Conference on Field-Programmable Logic and Applications. Pages 636 – 639, 2005.

[57]      U. Malik and O. Diessel. On the placement and granularity of FPGA configurations. In IEEE International Conference on Field-Programmable Technology (FPT’04), pages 161 – 168, 2004.

[58]      M. Guntsch, M. Middendorf, B. Scheuermann, O. Diessel, H. ElGindy, H. Schmeck, and K. So. Population based ant colony optimization on FPGA. In IEEE International Conference on Field-Programmable Technology (FPT’02), pages 125 – 132, 2002.

[59]      U. Malik, K. So and O. Diessel. Resource-aware run-time elaboration of behavioural FPGA specifications. In IEEE International Conference on Field-Programmable Technology (FPT’02), pages 68 – 75, 2002.

[60]      O. Diessel, U. Malik and K. So. Towards high-level specification, synthesis, and virtualization of programmable logic designs. In International Euro-Par Conference, pages 314 – 317, 2002.

[61]      O. Diessel and U. Malik. An FPGA interpreter with virtual hardware management. In Reconfigurable Architectures Workshop, IPDPS 2002 Abstracts, page 155, 2002.

[62]      G. Brebner and O. Diessel. Chip-based reconfigurable task management. In International Conference on Field-Programmable Logic and Applications, (FPL 2001), pages 182 – 191, 2001.

[63]      O. Diessel and G. Milne. Behavioural language compilation with virtual hardware management. In, International Workshop on Field–Programmable Logic and Applications, pages 707 – 717, 2000.

[64]      O. Diessel and G. Milne. Compiling process algebraic descriptions into reconfigurable logic. In Reconfigurable Architectures Workshop, IPDPS 2000, pages 916 – 923, 2000.

[65]      O. Diessel, D. Kearney and G. Wigley. A web–based multiuser operating system for reconfigurable computing. In Reconfigurable Architectures Workshop, IPPS/SPDP’99, pages 579 – 587, 1999.

[66]      O. Diessel and H. ElGindy. On scheduling dynamic FPGA reconfigurations. In Australasian Conference on Parallel and Real–Time Systems (PART’98), pages 191 – 200, 1998.

[67]      O. Diessel and H. ElGindy. Partial rearrangements of space–shared FPGAs (Extended abstract). In Reconfigurable Architectures Workshop, IPPS/SPDP’98, pages 913 – 918, 1998.

[68]      O. Diessel and H. ElGindy. Partial FPGA rearrangement by local repacking. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 259, 1998.

[69]      O. Diessel and H. ElGindy. Run–time compaction of FPGA designs. In International Workshop on Field–Programmable Logic and Applications, FPL’97, pages 131 – 140, 1997.

[70]      O. Diessel, H. ElGindy and B. Beresford-Smith. Partial task compaction reduces queuing delays in partitionable–array machines. In Australasian Conference on Parallel and Real–Time Systems, pages 186 – 194, 1996.

[71]      O. Diessel, H. ElGindy and L. Wetherall. Efficient broadcasting procedures for constrained reconfigurable meshes. In Australasian Conference on Parallel and Real–Time Systems, pages 85 – 88, 1996.

[72]      B. Beresford-Smith, O. Diessel and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes. In Australasian Computer Science Conference, pages 32 – 41, 1995.

[73]      B. Beresford-Smith, O. Diessel and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes (Extended abstract). In Australian Transputer and Occam User Group Conference, pages 28 – 39, 1994.

[74]      H. B. Penfold, O. F. Diessel and M. W. Bentink. A genetic breeding algorithm which exhibits self–organizing in neural networks. In International Symposium on A.I. Applications and Neural Networks, pages 293 – 296, 1990.

 

Editorials

 

[75]      L. Shannon, O. Diessel and N. Bergmann. Guest Editorial: Field-Programmable Technology, Journal of Signal Processing Systems, 67(1): 1 – 2, April 2012.

[76]      N. Bergmann, O. Diessel and L. Shannon, editors. Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT’09), IEEE Computer Society Press, 2009.

[77]      O. Diessel and J. A. Williams, editors. 2004 IEEE International Conference on Field-Programmable Technology (FPT’04). IEEE Computer Society Press, 2004.

 

Invited Talks

 

[78]      O. Diessel. Application, Design & Test of Dynamically Reconfigurable Field-Programmable Gate Array-based Systems. IET/IEEE/EA Joint Institutions Lecture, Engineers Australia, Harricks Auditorium, Sydney, 13 August 2015.

[79]      O. Diessel. Detecting and Mitigating Radiation-Induced Errors in SRAM-based Field-Programmable Gate Arrays. In 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI’2015), Qingdao, July 2015.

[80]      O. Diessel. Opportunities and Challenges for Dynamic FPGA Reconfiguration in Electronic Measurement and Instrumentation. In 11th IEEE International Conference on Electronic Measurement & Instruments (ICEMI’2013), Harbin, pages 266 – 271, 2013.

[81]      B. Hredzak and O. Diessel. Towards Dilated Placement of Dynamic NoC Cores. Dagstuhl Seminar on Dynamically Reconfigurable Architectures, Germany 2010.

[82]      O. Diessel. Moving Run-Time Reconfiguration into the Mainstream, Microelectronics Embedded Systems Workshop, Singapore 2007.

[83]      O. Diessel. Reconfigurable Computing, Infocomm Development Authority of Singapore, 2006.

[84]      O. Diessel and S. Koh. Enabling RTR for Industry, Dagstuhl Seminar on Dynamically Reconfigurable Architectures, Germany 2006.

[85]      O. Diessel. Towards High-Level Specification & Synthesis of Dynamic Process Logic, Dynamic Streaming Architectures Workshop, Caltech; Xilinx Research Labs; and University of Southern California, USA 2003.

[86]      O. Diessel. Operating Systems Support for Dynamically Reconfigurable Architectures, Dagstuhl Seminar on Reconfigurable Architectures, Germany 2000.

 

Workshop

 

[87]      O. Diessel, F. Engel, T. Percival and N. Temperley. Reconfigurable Computing Workshop, National ICT Australia, 2005

 

Technical Reports

 

[88]      M. Bernardi, E. Cetin and O. Diessel. Correct High Level Synthesis of Triple Modular Redundant User Circuits for FPGAs. Technical report UNSW-CSE-TR-201804, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, October 2018.

[89]      N.T.H. Nguyen, E. Cetin and O.Diessel. Scheduling Considerations for Voter Checking in FPGA-based TMR Systems. Technical report UNSW-CSE-TR-201705, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, March 2017.

[90]      S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. Technical report TR0603, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, February 2006.

[91]      U. Malik and O. Diessel. A Configuration Memory Architecture for Fast FPGA Reconfiguration. Technical report TR0509, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, April 2005.

[92]      J. Detrey and O. Diessel. A constructive proof of the Turing completeness of Circal. Technical report TR0214, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, September 2002.

[93]      J. Detrey and O. Diessel. SCCircal:  A static compiler mapping XCircal to Virtex FPGAs. Technical report TR0213, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, August 2002.

[94]      O. Diessel and G. Milne. HCircal:  A hardware compiler for Circal. Technical report ACRC–00–013, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Mawson Lakes, SA, Mar.  2000.

[95]      O. Diessel and G. Wigley. Opportunities for operating systems research in reconfigurable computing. Technical report ACRC–99–018, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Mawson Lakes, SA, Oct.  1999.

[96]      O. Diessel. On Scheduling Dynamic FPGA Reconfigurations — A Partial Rearrangement Approach. Ph.D. thesis, Department of Computer Science and Software Engineering, The University of Newcastle, Callaghan, Australia, Jan.  1998.

[97]      O. Diessel and H. ElGindy. Partial FPGA rearrangement by local repacking. Technical report 97–08, Department of Computer Science and Software Engineering, The University of Newcastle, Sept.  1997.

[98]      O. Diessel and H. ElGindy. Ordered partial task compaction on mesh connected computers. Technical report 96–11, Department of Computer Science and Software Engineering, The University of Newcastle, Sept.  1996.

[99]      O. Diessel. An investigation into the performance of a genetic algorithm for the selection of neural networks. B.E. project report, Department of Electrical Engineering and Computer Science, The University of Newcastle, Nov.  1990.

 

 

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