Since 2002, my group has been developing innovative learning techniques for medi cal images, including new incremental learning algorithms and innovative image a nalysis techniques for anatomy and feature extraction based on machine learning and knowledge acquisition. A prototype Computer Aided Diagnosis (CAD) system for automated diagnosis of diffuse lung diseases from CT images, integrating the ne w techniques has been developed. The medical imaging research was in collaborat ion with Medical Imaging Australasia as clinical and Philips Medical Systems Aus tralasia as industry partners.
In the area of motion tracking and segmentation, my group is working on tracking and recognition techniques suitable for immersive environments, as well as face tracking. Experiments are conducted at the iCinema centre. We have developed active vision techniques for an autonomous and adaptive security camera and a human motion classification system for it. Activity recognition is an ongoing area of research.
My group has made significant contributions to the field of formal modelling and analysis of concurrent real-time systems. We proposed a formal verification methodology y for Statecharts based on a customised temporal logic, published in IEEE Transactions on Software Engineering. My research group proposed a formal framework for automated hardware component reuse, based on an innovative technique called forced simulation invented by us, along with practical algorithms that automatically generate device drivers to adapt off-the-shelf components to match the requirements. The results were published i n ACM Transactions on Design Automation of Electronic Systems 2001. A more efficient algorithm for forced simulation using tabled logic programming was then developed and published in IEE Proceedings Computers and Digital Techniques. My group also developed automated interface synthesis techniques for mismatched protocols in VLSI chip design within a synchronous modelling framework, presented in IEE Proc. Computers and Digital Techniques in 2005. My group recently extended this work to deal with on-chip protocol incompatibility in general. A highly expressive formal modelling language for state-based communication synchronous protocols was developed, which allows modelling of modern industrial protocols at a level close to Hardware Design Languages but with better analysis capabilities. An algorithm to check for protocol incompatibility, and generate a small `converter' (converter synthesis) if necessary, has been designed. We have also developed methods for design space exploration to allow for converter optimization, which are the first in the field. My group has studied synchronous and asynchronous models of time and verificatio n techniques for these using timed automata. A Simulink block for the synchronou s language Argos was built and presented. A tool to perform time trace inclusion checking between multiple system implementations mo delled as timed automata has been built and released to the research community.