CASA 2007

Scope
This is the third edition of the CASA workshop (initially called OCASA) that brings together researchers and industrial attendees who want to teach, learn and discuss the use of compilers in designing SoC architectures. The goal of using compilers in the architecture design loop is to provide reliable information about the impact of architectural features. This reliable information is expected to avoid time-consuming design loops and is therefore expected to provide a "Drastic Reduction of NRE and Time-to-Market". The workshop will consist of invited university and industrial speakers performing high-profile research and development in the topic of the workshop title.
Programme (final schedule)

9:10 - 9:40 Wayner Wolf, (Georgia Tech, USA): Static vs. Dynamic in Embedded Software
9.40 - 10.10 Shuvra S. Bhattacharyya, (University of Maryland, USA): The Dataflow Interchange Format (DIF): a Framework for Specifying, Analyzing, and Integrating Dataflow Representations of DSP Systems
10.10 - 10.40 Joerg Henkel, (Karlsruhe University, Germany): RISPP: An Adaptive Embedded Processor

11.00 - 11.30 Carlos Tavares, Oskar Mencer and Wayne Luk, (Imperial College London): Accelerating assembly-level programs
11.30 - 12.00 Krishna V. Palem, (Rice University, USA): Significantly Improving Productivity in IP Reuse in Embedded Platform Design
12.00 - 12.30 Robert Dick, (Northwestern University, USA): Compiler-Assisted Memory Expansion for MMU-Less Embedded Systems

14.00 - 14.30 Guang Gao, (University of Delaware, USA): Multi-Core Chips Technology - A Fresh Look on Software Challenges
14.30 - 15.00 Tulika Mitra, (National University of Singapore, Singapore): A Compilation Framework for Customizable Processors
15.00 - 15.30 Kevin O'Brien, (IBM, USA): TBD
15.30 - 16.00 Hiroyuki Yagi, (Starc, Japan): STARC TL Modeling Guide

Grand Challenges to Compiler Technology in the MPSoC era