CASA 2007

The speakers are as follows,

Wayne Wolf - Georgia Tech, USA
- Static vs. Dynamic in Embedded Software
Compilers perform optimizations statically to improve software performance. Middleware mediates operations dynamically in multiprocessors. How do we decide what to do statically and what to do dynamically in an embedded system? This talk will consider various approaches to software architectures for embedded systems.

Carlos Tavares, Oskar Mencer and Wayne Luk - Imperial College London
- Accelerating assembly-level programs
Various techniques have been developed for partitioning an application into two parts: software running on an embedded processor, and hardware in a co-processor. Co-processors have been shown to be effective in accelerating applications for embedded systems. The embedded processor in such systems are often based on Reduced Instruction Set architectures. Recently system-on-chips based on Complex Instruction Set architectures such as x86 have been proposed. This talk addresses the challenges in accelerating assembly-level programs with complex instructions, making use of both static and dynamic analysis. We introduce an infrastructure to support assembly-level program manipulation, and describe its facilities such as those for instruction-level instrumentation.

Hiroyuki Yagi - Starc, Japan
- STARC TL Modeling Guide
As electronic designs become increasingly large and complicated, conventional RTL-based design flows have been facing a serious productivity crisis. To put past the limit of RTL design technology, Transaction-Level (TL) Modeling methodologies are being pursued as a new approach. Benefits of adopting TL modeling include concurrent hardware/software co-design from early in the design stages, quick architecture exploration and system-level performance analysis. Despite all these benefits, TL modeling is not widely used yet. There are several reasons why design teams procrastinate: 1) TL modeling is currently dependent on the design tool and language used; 2) there are interoperability issues between standards proposed by different standardization bodies in terms of the definitions of abstraction levels and communication APIs; 3) no clear guidelines are available for model structures and coding styles to ensure reusability. In light of this situation, the Semiconductor Technology Academic Research Center (STARC) in Japan has been working to develop guidelines regarding two things that have been big bottlenecks for the utilization of TLM: 1) definitions of abstraction levels and 2) model reusability. The STARC Transaction-Level (TL) Modeling Guide presents many code examples to help designers understand TLM better. The TL Modeling Guide will be a useful companion for a wide range of both those who are going to employ TLM and those who are already exploiting it.

Robert Dick - Department of Electrical Engineering and Computer Science, Northwestern University, USA
- Compiler-Assisted Memory Expansion for MMU-Less Embedded Systems
In some applications, MPSoC cost and power consumption constraints are so tight that even moderate-complexity applications are hampered. Random access memory (RAM) is tightly-constrained in the least expensive, lowest-power MPSoCs, such as the processors used in sensor network nodes. The most widely-used sensor network nodes have only 4-10 KB of RAM and do not contain memory management units (MMUs). It is difficult to implement complex applications under such tight memory constraints. Nonetheless, price and power consumption constraints make it unlikely that increases in RAM in these systems will keep pace with the memory requirements of applications.
We propose the use of automated compile-time and run-time techniques to increase the amount of usable memory in MMU-less embedded systems. The proposed techniques do not increase hardware cost, and require few or no changes to existing applications. We have developed run-time library routines and compiler transformations to control and optimize the automatic migration of application data between compressed and uncompressed memory regions, as well as a fast compression algorithm well suited to this application. These techniques were experimentally evaluated on Crossbow TelosB sensor network nodes running a number of data-collection and signal-processing applications.

Tulika Mitra - Department of Computer Science, National University of Singapore, Singapore
- A Compilation Framework for Customizable Processors
A customizable processor supports application-specific instruction-set extensions, also called custom instructions. Processors that allow such extensibility have become popular as they strike the right balance between challenging performance requirement and short time-to-market constraints of embedded systems design. The compiler plays a critical role in designing customizable processors. In this talk, we will present an efficient compilation framework that starts with an application specified in ANSI-C and automatically selects appropriate custom instructions.
Traditionally, the custom instructions selection process is guided by the application domain and its non-functional requirements such as performance, power, and area. However, current generation embedded systems impose additional hard-to-achieve requirements such as real-time constraints. The underlying architecture, on the other hand, may support novel features such as runtime reconfigurability of custom instructions. In this talk, we will describe how our compilation framework can select optimal design points by exploiting the architectural innovations while respecting the various constraints.

Shuvra S. Bhattacharyya - University of Maryland, College Park MD, USA
- The Dataflow Interchange Format (DIF): a Framework for Specifying, Analyzing, and Integrating Dataflow Representations of DSP Systems
This talk presents an overview of the dataflow interchange format (DIF) project at the University of Maryland. Dataflow models of computation are widely used in design automation for embedded digital signal processing (DSP) systems. A variety of DSP-oriented design tools incorporate dataflow semantics for system-level modeling, simulation, and synthesis. In addition, many off-the-shelf DSP libraries are available for various embedded processing platforms. Motivated by the heterogeneous capabilities of DSP design tools and libraries, we present a novel design language for DSP called the dataflow interchange format (DIF). DIF is designed specifically for helping DSP system designers integrate the diversity of dataflow-oriented models, techniques, design tools, libraries, and underlying processing platforms. DIF is designed as a standard language for specifying DSP-oriented dataflow graphs, and the associated "DIF framework" is an accompanying software tool that is designed to achieve the following objectives: 1) developing coarse-grain dataflow graph transformations and analysis techniques to explore the complex design spaces for embedded DSP systems; 2) porting DSP designs across various tools, libraries, and embedded processing platforms; and 3) experimenting with novel DSP-oriented dataflow models of computation and associated scheduling strategies.

Krishna V. Palem - Rice University, USA
- Significantly Improving Productivity in IP Reuse in Embedded Platform Design
Complex functionality required of embedded devices and increased transistor count afforded by successive technology generations, have increased the design and verification complexity, and consequently, increased the cost and time to market for such devices. Automation has been widely recognized as the the key to the reduction of cost and time to market. However, such automated approaches should not discard massive investments in legacy hardware IP. In this talk, we lay out a framework for increasing productivity in embedded system design, reducing cost and time to market with an emphasis on IP and software re-use and sketch future research directions.

Joerg Henkel - Chair for Embedded Systems, Karlsruhe University, Germany
- RISPP: An Adaptive Embedded Processor
Designing embedded processors becomes increasingly flexible since tool suites from major vendors allow the designer to customize in multiple ways including instruction set extensions. The designer faces then the problem to explore a large design space in order to find solutions that comply to given constraints (e.g. performance) with minimal area and/or minimal power consumption etc. The talk focuses on our RISPP processor platform. It is an adaptive extensible embedded processor that adjusts to varying constraints during rune time. Research is focused towards the question of what should be fixed at design time and what parts should be left flexible/adjustable at rune-time. Besides a prototype in form of an FPGA platform, a coupe of tools have been built in our lab to evaluate our approach. Though not limited to multi-media applications we demonstrate the functionality of RISPP by means of a video streaming application.

Kevin O'Brien - IBM
- TBD
...

Guang Gao - University of Delaware, USA
- Multi-Core Chips Technology - A Fresh Look on Software Challenges
In this talk, we discuss the challenges as well as opportunities facing software technology in the era of the emerging multi-core chip technology. We outline several fundamental performance issues facing system software designers while mapping parallel programs onto a class of multi-core architectures that do not employ data caches or on-chip MMUs.

Workshop Chair:
Sri Parameswaran, University of New South Wales, Australia