Sri Parameswaran

Impact of our work

1. Canon Information Systems Research Australia - Delivered a large software system for MPSoC designs

Patents generated:

  • US Patent 10,740,674 Layer-based operations scheduling to optimise memory for CNN applications
  • US Patent 10,684,776 Memory configuration for inter-processor communication in an MPSoC
  • US Patent 10,664,310 Memory access optimisation using per-layer computational mapping and memory allocation for CNN application
  • US Patent 9,477,799 Hierarchical determination of metrics for component-based parameterized SoCs
  • US Patent 8,018,928 Modular approach to the TCP/IPv6 hardware implementation
  • US Patent 7,672,694 Low power chip architecture 

2. Software for high speed bioinformatics - please see downloads page for details - these are now being used by a number of labs around the world

3. Did we chip into the creation of the latest Intel chip?

Sometime ago, a colleague sent an article about the much touted Next generation Intel Processors with Intel CET (Control Enforcement Technology) and asked whether this could be attacked. Having glanced at the article I was convinced that I had seen very similar technology before. Delving into my disheveled memory reminded me that Intel CET bears remarkable similarity to work performed by my then PhD student Roshan Ragel (now Professor of Computer Engineering at the University of Peradeniya, Sri Lanka) and I, in two papers published in 2005 (https://dl.acm.org/doi/abs/10.1145/1086297.1086337) and 2006 (https://ieeexplore.ieee.org/document/1688849). The first of these papers was also co-authored by Seyed Mohammad Kia (who was one of my early PhD students and was visiting us on a Sabbatical at that time and has recently retired in Canada). Seyed worked with us on clarifying and refining the ideas in the paper.

This was indeed a pleasant surprise, a proud moment where technology conceived  (or at the very least foreshadowed) in our very hands, nearly 15 years ago, had found life in probably the most widely used commodity microprocessor. Clearly there are some differences between our implementation from a decade and a half ago and Intel CET. Nonetheless, these differences are merely semantic and are briefly stated below.

One of the two features of Intel CET that provides return address protection is similar to our work  described in section 3.1 of the paper https://dl.acm.org/doi/abs/10.1145/1086297.1086337.  Both utilize a single instruction to push and pop return addresses into an additional stack to detect modifications of these addresses at runtime. The INTEL CET utilizes a software stack termed as “Shadow Stack” (and multiple of these due to enclaves), whereas we used a hardware stack (specialized stack in hardware which could not be manipulated by other instructions). Yet,  the underlying purpose of the call  and return  remains the same: the call pushes return addresses into two stacks and return pops  addresses from both stacks and compares them.

The second feature of Intel CET was to enable free branch protection, which involves the insertion of an instruction at all possible locations in the program where a branch or a jump instruction could legitimately reach. Thus, if an arbitrary address is reached then it is flagged and the program stops  its execution. A very similar technology was described by Roshan and I in https://ieeexplore.ieee.org/document/1688849 (Section 3). In Intel CET’s description, they reach an ENDBRRANCH instruction, whereas we reached a check instruction.

Moreover, while Intel CET only detects whether a branch reaches to an ENDBRANCH instruction, our check instruction additionally checked to see whether it actually arrived from the anticipated location.

Notwithstanding these minor differences, the similarities are indeed remarkable.

Did Intel know of our developments? We have every reason to believe so.

4. Processor Based FPGA Designs Capable of Continuously Executing in the Presence of Soft Errors - Delivered to Seeing Machines Inc.

These systems are deployed in millions of cars worldwide. It is anticipated that these would be in tens of millions of cars in the near future.

5. Pasindu Aluthwala's Chip

Pasindu Aluthwala, broke the “6 dB/bit rule”, a 67 year old popular signal processing limit.

Pasindu had been looking into designing area and power efficient on-chip digital sine-wave synthesizers for on-chip self-test, lab-on-chip, and communication system applications. The performance of conventional digital sine-wave synthesizers is bound by the “6 dB/bit” rule, but the research conducted by Pasindu  found that an alternate type of digital sine-wave synthesizers can perform up to 10.6 dB/bit with careful design.

To verify the findings Pasindu  successfully designed, fabricated, and tested a chip containing two different prototype circuits, using a 130 nm CMOS semiconductor process supported by STMicroelectronics.

Pasindu joins an exclusive club of chip designers who had their first chip working without any errors.

Pasindu was jointly supervised by CSE's Sri Parameswaran, Associate Prof. Torsten Lehmann (UNSW EET), Dr. Andrew Adams (Technical Director at Broadcom Inc) and Prof. Neil Weste.