Network on Chip (NoC) is the concept of integrating resources on a chip using on-chip routers. The on-chip routers perform packetization and routing similar to routers in couter networks. The key difference between on-chip routers and the routers in computer network is the router architecture. The on-chip router architecture is designed to increase throughput, improve quality of service by reducing packet loss and clock sycnhronization scheme.
The primary problems in realising a formal verification tool for NOC are: A modeling language that can co-specify hardware and software, specify both synchronous and asynchronous clocking strategies and has capability for realizing modules from specification. The research focuses on extending an existing formalism to model different types of clocking strategies and eventually model all the parameters of NoC and perform system-level verification using model checking .
Prof. Arcot Sowmya
Prof. Sridevan Parameswaran