This course builds on an understanding of Computer Organisation to allow advanced features of current general purpose and embedded processors to be appreciated. Related research themes in computer architecture are exposed. The course develops research and presentation skills through readings, presentations, and project work.
|Theme for 05s1:|
Processors are well adapted to the sequential von Neumann model of computation, which has limited scope for exploiting parallelism. Reconfigurable devices (such as FPGAs) perform well on repetitive computations that are easily implemented as circuits and are thus able to exploit parallelsm at the block, instruction, or sub-word level. The past decade has seen many attempts to bridge the gap between these models in the form of a reconfigurable microprocessor that includes both models within the one device. We shall study important contributions to this effort and examine current activity in the area.
After an initial study of instruction level parallelism and how it is exploited in modern microprocessors, our focus shifts to research literature from the fields of microarchitecture and reconfigurable computing to examine the merits of past and present designs for reconfigurable microprocessors.
|01||02/3||Oliver: Introduction||PPT, PDF|
|02||09/3||Oliver: Pipeline review; hazards||PPT, PDF||H&P, Appendix A
H&P, Ch. 3
|03||16/3||Oliver: Scoreboarding; Tomasulo's Algorithm||PPT, PDF||H&P, Appendix A.8
H&P, Ch. 3.2, 3.3
|04||23/3||Oliver: Branch prediction||PPT, PDF||H&P, Ch. 3.4, 3.5|
|05||06/4||Oliver: Multiple issue; Speculative execution||PPT, PDF||H&P, Ch. 3.6 - 3.10|
|06||13/4||Oliver: Software approaches to exploiting ILP||PPT, PDF||H&P, Ch. 4|
|07||20/4||Ben: From Sequences of Dependent Instructions to Functions, Yehia & Temam||PPT, PDF||ISCA04 paper|
|08||27/4||Oliver: FPGA Architecture overview (Virtex bias)||Virtex arch|
|Kynan: CHIMAERA Reconfigurable Functional Unit, Hauck et al.||PPT, PDF||ISCA00 paper|
|09||04/5||Senglin: Design Automation of Co-Processors for ASIPs||PPT, PDF|
|David: The WARP Processor: Dynamic HW/SW Partitioning, Vahid et al.||PPT, PDF||ICCAD02 paper|
|10||11/5||Jeremy: Networks on chip: A very quick introduction||PPT, PDF|
|Jiening: A design space evaluation of Grid Processor Architectures, Nagarajan et al.||PPT, PDF||MICRO01 paper|
|11||18/5||Lih Wen: Reconfigurable Microprocessors||PPT, PDF||ACSAC04 inspiration|
|James: Cell Processor, Hofstee||PPT (huge!), PDF (huge!)||HPCA05 paper
more Cell details
|13||01/6||Shannon: Communication support for task-based runtime reconfiguration in FPGAs||PPT, PDF|
|Usama: Systems and techniques for fast FPGA reconfiguration||PPT, PDF|
Ben: Hardware managed scratchpad for embedded systems
Jiening: Network processor
David: Handling branches through context forking
Kynan: Microblaze running uClinux
James: Resonant tunnelling devices
Assessment in this course will be based on:
A 1 hour seminar is to be given on one of the papers from the reading list. You may choose the paper that interests you most, but selection is on a first-come, first-served basis. The presentation will be assessed for quality (slides, presentation skill, ability to convey ideas), thoroughness, and ability to answer questions.
A brief project proposal (about 1/2 page) is to be developed by the student and agreed to by the LiC. The proposal will contribute 5 of the 60 marks for the project. Note to LiC: in future, place time limit of 5th week on completing this objective.
A brief presentation (of about 15-20 mins) is to be given in Week 14 and cover the motivation, methodology, results, and conclusion. This presentation will contribute 15/60 marks.
A 10 - 20 page report on the project is to be prepared by 17 June, 2005. The report will be assessed for the completeness and understandability of your motivations, design, implementation, results, and conclusions. It will contribute 40 marks to the total project mark.
A seminar log is to be kept, and this will be marked at the conclusion of the course. Students are expected to actively contribute to class discussions. It is recommended that students prepare by reading material to be presented prior to class.
The main component of the assessment in COMP4211 is derived from the project. It is expected that the project will require approximately 80 - 100 hours of commitment from the student. Ideally, the student proposes a project and refines the proposal in consultation with the LiC. This allows the student to pursue his or her interests in computer architecture. There is an expectation that if the project is related to other work being performed for credit e.g. thesis, there is sufficient separation between the outcomes sought for the COMP4211 project and the other work. Nevertheless, we do not intend to discourage overlap. The COMP4211 project should be limited in scope such that the entire project can be completed within the 80 - 100 hours allocated.
Project proposals should be negotiated with the LiC before Easter in 2005.
Oliver Diessel, K17-502, Ext. 55922.