05s1
COMP4211 Adv. Architectures Reading List
- S. Jourdan, P. Sainrat, and D. Litaize. Exploring
Configurations of Functional Units in an Out-Of-Order Superscalar
Processor. In 22nd International Symposium on Computer Architecture,
pages 117--124, June 1995.
- S.
Yehia and O. Temam. From sequences of dependent instructions to
functions: An approach for improving performance without ILP or
speculation. In Proc. ISCA04, pp 238 249. IEEE, 2004.
- Z.
A. Ye, A. Mashovos, S. Hauck, and P. Banerjee. CHIMAERA: A high-performance
architecture with a tightly-coupled reconfigurable functional unit. In
Proc. 27th Intl Symp. On Comp. Arch. (ISCA00), pages 225
235. ACM 2000.
- S.
Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. The Chimaera
reconfigurable functional unit. IEEE Trans. VLSI Syst., 12(2), pages
206 217. Feb. 2004.
- Warp Processors. See http://www.cs.ucr.edu/~vahid/warp/
- G. Stitt and F. Vahid. Hardware/Software
Partitioning of Software Binaries. IEEE/ACM International Conference
on Computer Aided Design (ICCAD), pp. 164 170, Nov. 2002.
- U. Nageldinger. Coarse-grained
Reconfigurable Architectures Design Space Exploration. Chapter 2, PhD
Dissertation, 2001.
- R.
Nagarajan, K. Sankaralingam, D. Burger, and S. W. Keckler. A design
space evaluation of grid processor architectures. In Proc. 34th
Annual Intl Symp. On Microarchitecture, pages 40 51. IEEE, 2001.
- K.
Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D.C. Burger, S.W.
Keckler, and C.R. Moore. Exploiting ILP,TLP, and DLP with the
Polymorphous TRIPS Architecture. Proceedings
of the 30th Annual International Symposium on Computer Architecture
(ISCA), June, 2003.
- M.
Epalza, P. Ienne, and D. Mlynek. Dynamic reallocation of functional
units in superscalar processors. In Proc. ACSAC 2004, LNCS 3189, pages
185 198. Springer-Verlag, 2004.
- B. F. Veale, J. K. Antonio, and M. P.
Tull. Architectural approaches
for dynamic translation and reconfiguration. Region 5
Conference: Annual Technical and Leadership Workshop, pages 49 58. IEEE,
2004.