2022 COMP4601 Seminars (Release: 25/05/2022, Edited: 11/07/2022)

Instructions

Seminar topics will be presented in groups of 3 people in the order shown below during weeks 7-10. A poll has been set up on Moodle for you to indicate your preference for the topic you would like to be involved in presenting. The poll will be available from 5 pm, Thursday 9 June. Note that preferences are accepted in first-come, first-served order. You have one vote, which you may change until the poll closes. When 3 people have selected a topic, that topic will no longer be available for selection. Please make your selection by 9am, Monday 20 June.

Seminars on the given topics are to be prepared and presented as a group. Between one and three papers have been _suggested_ as resources from which to prepare an interesting, integrated and coordinated presentation on your understanding of the topic. Please take note that you are not expected to present all of the material in the papers that have been recommended for a topic, rather, you should focus on preparing what you consider to be an interesting, complete and coordinated presentation on some aspect(s) of the seminar topic. You may also draw on other materials to prepare your presentations if you wish. Please contact Oliver should you need further guidance.

You are required to prepare and email Oliver in PDF form a 1-2 page Executive Summary of your seminar topic by 5pm on the Monday before your seminar. These will be made available for the audience members to be able to prepare themselves for your presentations.

A PDF copy of your seminar presentation is to be emailed to Oliver by 5pm on the Tuesday before your seminar. This copy will be made available online for reference during your presentation, discussion and evaluation. Please email Oliver an updated version of the file after your seminar presentation if you make any further changes to it.

Seminar presentations are expected to involve a 5-10 minute individual presentation by each member of the seminar group. This will be followed by a brief discussion during which the group may like to further comment on their topic and should be prepared to respond to questions from the audience. The total time allowed for your seminar is approximately 40 mins. Seminar presentations may be recorded.

Audience members will use the course Seminar Evaluation Form to score the seminar presentations and excutive summaries. One form is to be completed for each seminar topic attended by the student. These forms are to be submitted at the conclusion of each week's seminar using the seminar submission page on the course website.

Individual presentations will contribute 10% to your final mark in the course. Expect to allocate 10-20 hours time preparing your seminar presentation. Audience members will be awarded up to 10% of their final mark for their participation in providing meaningful evaluations of the seminars they did not present, as well as their contributions to discussions.

Some of the seminar topics include copies of the 2021 executive summary and presentation slides, while the remainder unfortunately don't have such presentation examples to draw upon. The course staff feel these materials provide some guidance that assists in the preparation of the seminar and will take this difference into consideration when marking.

2022 Seminar Topics & Presentations

A. High-level Synthesis (Week 7)

1. Cong, Jason, Bin Liuy, Stephen Neuendorffer, Juanjo Noguera, Kees Vissers, and Zhiru Zhang. "High-Level Synthesis for FPGAs: From Prototyping to Deployment." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 30, no. 4 (2011): 473-491.

2. Canis, Andrew, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz Czajkowski, Stephen D. Brown, and Jason H. Anderson. "LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems." ACM Transactions on Embedded Computing Systems (TECS) 13, no. 2 (2013): 24.

• Zhongtao Hu
• Davit Melkumyan
• Liang Peng

• Junkang Chen
• Yuanzhi Shang
• Xukun Zhong

B. Architectural Synthesis (Week 7)

3. De Micheli, Giovanni. " Architectural Synthesis." In Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

• Ezra Hui
• Arpit Rulania
• Alexander Wan

• Ewan Barnett
• Adam Florence
• George Litsas

C. Technology Mapping (Week 7)

4. Cong, Jason, and Yuzheng Ding. "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 13, no. 1 (1994): 1-12.

• Eric Lin
• Aphisit Udompolvanich
• Sawat Wongsaroj

D. FPGA Routing (Week 7)

5. McMurchie, Larry, and Carl Ebeling. "PathFinder: a negotiation-based performance-driven router for FPGAs." In Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, pp. 111-117. ACM, 1995.

• Feddrick Aquino
• Saurabh Jain
• Tarandeep Panesar

E. Reconfigurable Devices (Week 8)

6. Tessier, Russell, Kenneth Pocek, and Andre DeHon. "Reconfigurable computing architectures." Proceedings of the IEEE 103, no. 3 (2015): 332-354.

7. Xilinx, Inc. "Zynq-7000 SoC Data Sheet: Overview." Product Specification DS190 (v1.11.1) July 2, 2018.

• Dong Huang
• Tirth Parikh
• Mukul Sharma

• Meg Bommena
• Quynh Boi Phan
• Jasmine Young

F. Reconfigurable Computing (Week 8)

8. Katherine Compton and Scott Hauck. "Reconfigurable computing: a survey of systems and software." ACM Comput. Surv. 34, 2 (June 2002), 171-210.

9. DeHon, André, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael Vanier, and Michael Wrighton. "Design patterns for reconfigurable computing." In Field-Programmable Custom Computing Machines, 2004. FCCM 2004. 12th Annual IEEE Symposium on, pp. 13-23. IEEE, 2004.

• Neel Bhaskar
• Raymond Soedargo
• Gabriel Tay Wei Chern

• Yazed Alfahi
• Oscar Downing
• Suphachabhar Nigrodhananda

G. Runtime Reconfiguration (Week 8)

10. Papadimitriou, Kyprianos, Apostolos Dollas and Scott Hauck. " Performance of partial reconfiguration in FPGA systems: A survey and a cost model." ACM Transactions on Reconfigurable Technology and Systems, 4, no. 4 (2011): 1-24.

11. Wirthlin, Michael J. and Brad L. Hutchings. "Improving Functional Density Using Run-Time Circuit Reconfiguration." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 6, no. 2 (1998): 247-256.

• Louisa Canepa
• Malavika Pasupati
• Andrew Wong

• Braydon Reitano
• Khang Trinh
• Alice Yu

H. Custom Processors (Week 8)

12. Galuzzi, Carlo, and Koen Bertels. " The Instruction-Set Extension Problem: A Survey." ACM Transactions on Reconfigurable Technology and Systems, 4, no. 2 (2011): 1-28.

13. Al Kadi, Muhammed, Benedikt Janssen, Jones Yudi, Michael Huebner. " General-Purpose Computing with Soft GPUs on FPGAs." ACM Transactions on Reconfigurable Technology and Systems, 11, no. 1 (2018): 1-22.

• Rea Agrawal
• Bassam Albaydani
• Sean Watt

I. Neural Network Accelerators (Week 9)

14. Guo, Kaiyuan, Shulin Zeng, Jincheng Yu, Yu Wang and Huazhong Yang." A Survey of FPGA-based Neural Network Inference Accelerators." ACM Transactions on Reconfigurable Technology and Systems, 12, no. 1 (2019): 1-26.

15. Liu, Zhiqiang, Yong Dou, Jingfei Jiang, Jinwei Xu, Shijie Li, Yongmei Zhou and Yingnan Xu. " Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks." ACM Transactions on Reconfigurable Technology and Systems, 10, no. 3 (2017): 1-23.

• Shi Tong Yuan
• Michael Zhang
• Yuanjie Zhang

• Cheng Jiang
• Yuedong Li
• Xinpei Zhang

J. Large-scale Sorting (Week 9)

16. Jun, Sang-Woo, and Shuotao Xu. "Terabyte sort on FPGA-accelerated flash storage." In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 17-24. IEEE, 2017.

17. Manev, Kristiyan, and Dirk Koch. "Large utility sorting on FPGAs." In 2018 International Conference on Field-Programmable Technology (FPT), pp. 334-337. IEEE, 2018.

• Wenyao Chen
• Jackie Deng
• Mingxuan Yu

K. Graph Processing using FPGAs (Week 9)

18. Zhou, Shijie, Charalampos Chelmis, and Viktor K. Prasanna. "Accelerating large-scale single-source shortest path on FPGA." In 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, pp. 129-136. IEEE, 2015.

19. Zhou, Shijie, Charalampos Chelmis, and Viktor K. Prasanna. "High-throughput and energy-efficient graph processing on FPGA." In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 103-110. IEEE, 2016.

• Kanit Srihakorth
• Jingtian Wei
• Zhengda Zhong

L. Packet Processing (Week 9)

20. Attig, Michael, and Gordon Brebner. "400 Gb/s programmable packet parsing on a single FPGA." In 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems, pp. 12-23. IEEE, 2011.

21. Brebner, Gordon, and Weirong Jiang. "High-speed packet processing using reconfigurable computing." IEEE Micro 34, no. 1 (2014): 8-18.

• Christopher Ka-Fai Lee
• James Tran
• Abrar Zaman

M. Datacentre Acceleration (Week 10)

22. Kachris, Christoforos, and Dimitrios Soudris. "A survey on reconfigurable accelerators for cloud computing." In Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, pp. 1-10. IEEE, 2016.

23. Putnam, Andrew, Adrian M. Caulfield, Eric S. Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh et al. "A reconfigurable fabric for accelerating large-scale datacenter services." In Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on, pp. 13-24. IEEE, 2014.

24. Caulfield, Adrian M., Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil et al. "A cloud-scale acceleration architecture." In Microarchitecture (MICRO), 2016 49th Annual IEEE/ACM International Symposium on, pp. 1-13. IEEE, 2016.

• Tvisha Kubal
• Khaing Myat Noe Naing
• Farnaz Tavakol

• Daniel Rosengarten
• Elton Shi
• Wei Leong Soon

N. End of Moore's Law? (Week 10)

25. Thompson, Neil C. and Svenja Spanuth. " The Decline of Computers as a General Purpose Technology." Communications of the ACM, 64, no. 3 (2021): 64-72.

26. Hill, Mark D., and Michael R. Marty. "Amdahl's law in the multicore Era." Univ. of Wisconsin computer sciences technical report CS-TR-2007-1593. (2007). (IEEE Computer article)

• Ziyue Lian
• Vincent Liu
• Jiacheng Lu

• Yifan Wang
• Youcheng Zhang
• Yunrui Zhang

Reading list

• Kirkpatrick, Scott, and M. P. Vecchi. "Optimization by simulated annealing." Science Vol. 220 No. 4598 (1983): 671-680.

• Purnaprajna, Madhura, Marek Reformat and Witold Pedrycz. "Genetic algorithms for hardware-software partitioning and optimal resource allocation." Journal of Systems Architecture, 53 (2007) 339-354.

• Thompson, Adrian. "An evolved circuit, intrinsic in silicon, entwined with physics." In Evolvable Systems: From Biology to Hardware, pp. 390-405. Springer Berlin Heidelberg, 1997.

• Huelsbergen, Lorenz. "A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms." In Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, pp. 105-115. ACM, 2000.

• Asanovic, Krste, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson et al. The landscape of parallel computing research: A view from Berkeley. Vol. 2. Technical Report UCB/EECS-2006-183, EECS Department, University of California, Berkeley, 2006.

• Ian Kuon, Russell Tessier, and Jonathan Rose. "FPGA Architecture: Survey and Challenges." Found. Trends Electron. Des. Autom. 2, 2 (February 2008), 135-253.

• Nane, Razvan, Vlad-Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen et al. "A survey and evaluation of fpga high-level synthesis tools." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 10 (2016): 1591-1604.

• Betz, Vaughn, and Jonathan Rose. "VPR: A new packing, placement and routing tool for FPGA research." In Field-Programmable Logic and Applications, pp. 213-222. Springer Berlin Heidelberg, 1997.

• Zhang, Jiliang and Gang Qu. " Recent Attacks and Defenses on FPGA-based Systems." ACM Transactions on Reconfigurable Technology and Systems, 12, no. 3 (2019): 1-24.

• Ziener, Daniel, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schuerfeld, Juergen Teich, Joerg-Stephan Vogt and Helmut Weber. " FPGA-Based Dynamically Reconfigurable SQL Query Processing." ACM Transactions on Reconfigurable Technology and Systems, 9, no. 4 (2016): 1-24.

• Ho, Chun Hok, ChiWai Yu, Philip Leong, Wayne Luk, and Steven JE Wilton. "Floating-point FPGA: architecture and modeling." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 17, no. 12 (2009): 1709-1718.