School of Computer Science & Engineering
University of New South Wales
Advanced Operating Systems
COMP9242 2002/S2
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- Use a hierarchy of caches to balance memory accesses:
- Small, fast, virtually indexed cache on top (L1 cache).
- Large, slow, physically indexed cache at bottom (L2-L5).
- Each level reduces and clusters traffic.
- High levels tend to be separated into instruction and data caches.
- Low levels tend to be unified.
Gernot Heiser
2002-08-15