Advanced Operating Systems
COMP9242 2002/S2
UNSW
Printer-Friendly Version
Administration
-
Notices
-
Course Intro
-
Consultations
# On-line Survey (closed)
-
Survey Results
Work
-
Lectures
-
Milestone 0
-
Project Admin
-
Project Spec
-
Project FAQ
-
Exam
Documentation
-
ASysT Lab
-
L4 source browser
-
Sulima ISA Simulator
-
R4x00 ISA Summary
-
MIPS R4700 Reference
-
MIPS R4000 User Manual
-
Network Driver
-
GT64111
Related Info
-
Aurema OS Prize
-
OS Hall of Fame
History
-
2000
-
1999
-
1998
Staff
-
Gernot Heiser
(LiC)
Next:
Other Memory Models
Up:
10-smp
Previous:
Effects of Memory Architecture
Memory Models: Strong Ordering
Loads and stores executed
in program order
.
Memory accesses of different CPUs are sequentialised.
Traditionally used by many architectures.
CPU 0
store
r1, adr1
load
r2, adr2
CPU 1
store
r1, adr2
load
r2, adr1
At least one CPU must load the other's new value.
Gernot Heiser 2002-10-11