Design, implement and assess an efficient Compressed-VA addressing scheme for Xilinx Virtex FPGA configuration memory. Tech report UNSW-CSE-TR0509 decribes Vector Addressing (VA) and its implementation. Compressed VA involves compressing the address map and decompressing this on chip.
Survey memory addressing schemes suited to Xilinx Virtex FPGA sub-frame addressing. See tech report UNSW-CSE-TR0509 for a description of the problem and one approach, vector addressing.
Consider paper number 10 from the reading list. Look at reconfiguration of a floating point ALU into extra integer ALUs and vice-versa. What's involved? How do you do it? What are the costs/benefits?
Write a research essay on the state of play in nano-scale computing, quantum computing, or molecular computing.
Contribute to the implementation of a VHDL model of the out-of-order SimpleScalar simulator.
Contribute to the analysis of program traces to assess performance benefits of reconfigurable functional units.