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Oliver Diessel

 

Senior Lecturer

School of Computer Science and Engineering

University of New South Wales

UNSW SYDNEY NSW 2052 AUSTRALIA

 

Office: K17-501B

Tel: +61 2 9385 7384

Fax: +61 2 9385 5995

 

Email: odiessel@cse.unsw.edu.au

 

Infopage: https://www.cse.unsw.edu.au/db/staff/staff_details.php?ID=odiessel

 

Career: http://www.ichoosetechnology.com.au/

 

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Keywords

 

 

Research Goals

 

Reconfigurable computing is concerned with adapting a system's hardware and software to cope with run-time changes in functional  or performance requirements, resource availability, and component failure. The main challenge is to find solutions to on-line design problems. Specific areas of interest include: the specification and automatic synthesis of optimal hardware configurations; run-time environments for dynamically reconfigurable systems; and optimising applications using reconfigurable technology.

 

Ongoing Projects

 

 

Past Projects

 

 

 

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Research Project Openings for Prospective Students

 

 

This project involves the development of techniques to bound the maximum time needed for FPGA-based implementations of Triple Modular Redundant systems to recover from radiation-induced Single Event Upsets. We are investigating design approaches, CAD tools for circuit partitioning and layout, and benchmarking with circuits typical of applications deployed in space.

 

 

Computational tasks hosted on FPGA devices are increasingly susceptible to run-time errors due to process variation, device degradation and radiation. This project seeks to develop efficient (better than TMR) techniques for checking the correctness of tasks while they are running. Another thrust is to validate dynamically acquired FPGA configurations.

 

 

ReSim is a simulation library for verifying partially reconfigurable designs. The object of this work is to extend ReSim to support the verification of

 

 

Please email me to discuss these opportunities futher.

 

PhD Students

 

 

Masters Students

 

 

Visiting Students

 

 

Project Students

 

 

 

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Configurable Systems

 

 

Computer Architecture

 

 

Digital Systems

 

 

Computer Programming

 

 

Professional Issues & Ethics

 


 

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Professional Activities        Research    Students    Teaching    Administration    Publications    Personal    Home   

 

Editorial Board Member

 

 

Recent Organizing Roles

 

 

Program Committee Member

 

 
 

Publications        Research    Students    Teaching    Administration    Profession    Personal    Home   

 

Journal Publications

 

[1]          L. Gong and O. Diessel. Simulation-based Functional Verification of Dynamically Reconfigurable Systems. ACM Transactions on Embedded Computing Systems, 13(4): Article 97, 23 pages, February 2014.

[2]          S. Koh and O. Diessel. Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration. ACM Transactions on Reconfigurable Technology and Systems, 3(1): Article 4, January 2010.

[3]          B. Scheuermann, K. So, M. Guntsch, M. Middendorf, O. Diessel, H. ElGindy, and H. Schmeck. FPGA implementation of population-based ant colony optimization. Applied Soft Computing, Special Issue on Hardware Implementation of Soft Computing Techniques, 4(3): 303 – 322, August 2004.

[4]          O. Diessel and H. ElGindy. On dynamic task scheduling for FPGA–based systems. International Journal of Foundations of Computer Science, Special Issue on Scheduling:  Theory and Applications, 12(5): 645 – 669, October 2001.

[5]          O. Diessel and G. Milne. A hardware compiler realizing concurrent processes in reconfigurable logic. IEE Proceedings — Computers and Digital Techniques, 148(4): 152 – 162, September 2001.

[6]          O. Diessel, H. ElGindy, M. Middendorf, H. Schmeck, and B. Schmidt. Dynamic scheduling of tasks on partially reconfigurable FPGAs. IEE Proceedings — Computers and Digital Techniques, Special Issue on Reconfigurable Systems, 147(3): 181 – 188, May 2000.

[7]          B. Beresford-Smith, O. Diessel, and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes. Journal of Parallel and Distributed Computing, 39(1): 74 – 78, November 1996.

 

Conference Papers

 

[8]          E. Cetin, O. Diessel, L. Gong, V. Lai. Reconfiguration Network Design for SEU Recovery in FPGAs. To appear International Symposium on Circuits and Systems (ISCAS), 2014.

[9]          E. Cetin, O. Diessel, L. Gong, V. Lai. Towards Bounded Error Recovery Time in FPGA-based TMR Circuits Using Dynamic Partial Reconfiguration. In 23rd International Conference on Field-Programmable Logic and Applications (FPL), 2013.

[10]       L. Gong, O. Diessel, J. Paul, and W. Stechele, RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study. In Parallel and Distributed Processing, International Symposium on, Reconfigurable Architecture Workshop (RAW), pages 106 – 113, 2013.

[11]       E. Cetin and O. Diessel, Guaranteed Fault Recovery Time for FPGA-based TMR Circuits Employing Partial Reconfiguration. In 2012 DAC Workshop 2nd International Workshop on Computing in Heterogeneous, Autonomous ‘N’ Goal-oriented Environments (CHA’N’GE), 2012.

[12]       L. Gong and O. Diessel, Functionally Verifying State Saving & Restoration in Dynamically Reconfigurable Systems. In 2012 ACM/SIGDA International Symposium on FPGAs (FPGA’12), pages 241 – 244, 2012.

[13]       L. Gong and O. Diessel, ReSim: A Reusable Library for RTL Simulation of Dynamic Partial Reconfiguration. In 2011 International Conference on Field-Programmable Technology (FPT’11), pages 1 – 8, 2011.

[14]       B. Hredzak and O. Diessel, Optimization of Placement of Dynamic Network-on-chip Cores Using Simulated Annealing. In 37th Annual Conference of the IEEE Industrial Electronics Society (IECON 2011), pages 2400 – 2405, 2011.

[15]       L. Gong and O. Diessel, Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’11), pages 9 – 16, 2011.

[16]       B. Kwek, F. Sunarso, M. Teoh, A. van Zal, P. Preston, and O. Diessel, FPGA-Based Video Processing for a Vision Prosthesis. In 2010 International Conference on Field-Programmable Technology (FPT’10), pages 345 – 348, 2010.

[17]       V. Lai and O. Diessel, ICAP-I: A Reusable Interface for the Internal Reconfiguration of Xilinx FPGAs. In 2009 International Conference on Field-Programmable Technology (FPT’09), pages 357 – 360, 2009.

[18]       J.Y.-C. Kuo, A.K-A. Ku, J. Xue, O. Diessel, and U. Malik. ACS: An Addressless Configuration Support for Efficient Partial Reconfigurations. In 2008 International Conference on Field-Programmable Technology (FPT2008), pages 161 – 168, 2008.

[19]       S. Koh and O. Diessel. The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration. In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’08), pages 65 – 76, 2008.

[20]       U. Malik, O. Diessel, and A. Dempster. Fast Code-Phase Alignment of GPS Signals using Virtex-4 FPGAs. In International Global Navigation Satellite Systems (IGNSS), 2007.

[21]       S. Koh and O. Diessel, Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. In International Conference on Field Programmable Logic and Applications (FPL’07), pages 293 – 298, 2007.

[22]       S. Koh and O. Diessel. Communications Infrastructure Generation for Modular FPGA Reconfiguration. In IEEE International Conference on Field-Programmable Technology (FPT2006), pages 321 – 324, 2006.

[23]       L.W. Koh and O. Diessel. Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. In Asia-Pacific Computer Systems Architecture Conference (ACSAC), pages 161 – 174, 2006.

[24]       U. Malik and O. Diessel. The Entropy of FPGA Reconfiguration. In International Conference on Field Programmable Logic and Applications (FPL’06), pages 261 – 266, 2006.

[25]       S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs (Extended Abstract). In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’06), pages 273 – 274, 2006.

[26]       S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. In International Conference on Architecture of Computing Systems, Workshops Proceedings, pages 173 – 182, 2006.

[27]       M. Della Torre, U. Malik, and O. Diessel. A configuration system architecture supporting bit-stream compression for FPGAs. In Asia-Pacific Computer Systems Architecture Conference, pages 415 – 428, 2005.

[28]       U. Malik and O. Diessel. A Configuration memory architecture for fast run-time reconfiguration of FPGAs. In International Conference on Field-Programmable Logic and Applications. Pages 636 – 639, 2005.

[29]       U. Malik and O. Diessel. On the placement and granularity of FPGA configurations. In IEEE International Conference on Field-Programmable Technology (FPT’04), pages 161 – 168, 2004.

[30]       M. Guntsch, M. Middendorf, B. Scheuermann, O. Diessel, H. ElGindy, H. Schmeck, and K. So. Population based ant colony optimization on FPGA. In IEEE International Conference on Field-Programmable Technology (FPT’02), pages 125 – 132, 2002.

[31]       U. Malik, K. So, and O. Diessel. Resource-aware run-time elaboration of behavioural FPGA specifications. In IEEE International Conference on Field-Programmable Technology (FPT’02), pages 68 – 75, 2002.

[32]       O. Diessel, U. Malik, and K. So. Towards high-level specification, synthesis, and virtualization of programmable logic designs. In International Euro-Par Conference, pages 314 – 317, 2002.

[33]       O. Diessel and U. Malik. An FPGA interpreter with virtual hardware management. In Reconfigurable Architectures Workshop, IPDPS 2002 Abstracts, page 155, 2002.

[34]       G. Brebner and O. Diessel. Chip-based reconfigurable task management. In International Conference on Field-Programmable Logic and Applications, (FPL 2001), pages 182 – 191, 2001.

[35]       O. Diessel and G. Milne. Behavioural language compilation with virtual hardware management. In, International Workshop on Field–Programmable Logic and Applications, pages 707 – 717, 2000.

[36]       O. Diessel and G. Milne. Compiling process algebraic descriptions into reconfigurable logic. In Reconfigurable Architectures Workshop, IPDPS 2000, pages 916 – 923, 2000.

[37]       O. Diessel, D. Kearney, and G. Wigley. A web–based multiuser operating system for reconfigurable computing. In Reconfigurable Architectures Workshop, IPPS/SPDP’99, pages 579 – 587, 1999.

[38]       O. Diessel and H. ElGindy. On scheduling dynamic FPGA reconfigurations. In Australasian Conference on Parallel and Real–Time Systems (PART’98), pages 191 – 200, 1998.

[39]       O. Diessel and H. ElGindy. Partial rearrangements of space–shared FPGAs (Extended abstract). In Reconfigurable Architectures Workshop, IPPS/SPDP’98, pages 913 – 918, 1998.

[40]       O. Diessel and H. ElGindy. Partial FPGA rearrangement by local repacking. In ACM/SIGDA International Symposium on Field Programmable Gate Arrays, page 259, 1998.

[41]       O. Diessel and H. ElGindy. Run–time compaction of FPGA designs. In International Workshop on Field–Programmable Logic and Applications, FPL’97, pages 131 – 140, 1997.

[42]       O. Diessel, H. ElGindy, and B. Beresford-Smith. Partial task compaction reduces queuing delays in partitionable–array machines. In Australasian Conference on Parallel and Real–Time Systems, pages 186 – 194, 1996.

[43]       O. Diessel, H. ElGindy, and L. Wetherall. Efficient broadcasting procedures for constrained reconfigurable meshes. In Australasian Conference on Parallel and Real–Time Systems, pages 85 – 88, 1996.

[44]       B. Beresford-Smith, O. Diessel, and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes. In Australasian Computer Science Conference, pages 32 – 41, 1995.

[45]       B. Beresford-Smith, O. Diessel, and H. ElGindy. Optimal algorithms for constrained reconfigurable meshes (Extended abstract). In Australian Transputer and Occam User Group Conference, pages 28 – 39, 1994.

[46]       H. B. Penfold, O. F. Diessel, and M. W. Bentink. A genetic breeding algorithm which exhibits self–organizing in neural networks. In International Symposium on A.I. Applications and Neural Networks, pages 293 – 296, 1990.

 

Editorials

 

[47]       L. Shannon, O. Diessel, and N. Bergmann, Guest Editorial: Field-Programmable Technology, Journal of Signal Processing Systems, 67(1): 1 – 2, April 2012.

[48]       N. Bergmann, O. Diessel, and L. Shannon, editors. Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT’09), IEEE Computer Society Press, 2009.

[49]       O. Diessel and J. A. Williams, editors. 2004 IEEE International Conference on Field-Programmable Technology (FPT’04). IEEE Computer Society Press, 2004.

 

Invited Talks

 

[50]       O. Diessel. Opportunities and Challenges for Dynamic FPGA Reconfiguration in Electronic Measurement and Instrumentation. In 11th IEEE International Conference on Electronic Measurement & Instruments (ICEMI’2013), pages 266 – 271, 2013.

[51]       B. Hredzak and O. Diessel, Towards Dilated Placement of Dynamic NoC Cores. Dagstuhl Seminar on Dynamically Reconfigurable Architectures, Germany 2010.

[52]       O. Diessel. Moving Run-Time Reconfiguration into the Mainstream, Microelectonics Embedded Systems Workshop, Singapore 2007

[53]       O. Diessel. Reconfigurable Computing, Infocomm Development Authority of Singapore, 2006

[54]       O. Diessel and S. Koh. Enabling RTR for Industry, Dagstuhl Seminar on Dynamically Reconfigurable Architectures, Germany 2006

[55]       O. Diessel. Towards High-Level Specification & Synthesis of Dynamic Process Logic, Dynamic Straming Architectures Workshop, Caltech; Xilinx Research Labs; and University of Southern California, USA 2003

[56]       O. Diessel. Operating Systems Support for Dynamically Reconfigurable Architectures, Dagstuhl Seminar on Reconfigurable Architectures, Germany 2000

 

Workshop

 

[57]       O. Diessel, F. Engel, T. Percival, and N. Temperley. Reconfigurable Computing Workshop, National ICT Australia, 2005

 

Technical Reports

 

[58]       S. Koh and O. Diessel. COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. Technical report TR0603, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, February 2006.

[59]       U.Malik and O.Diessel. A Configuration Memory Architecture for Fast FPGA Reconfiguration. Technical report TR0509, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, April 2005.

[60]       J. Detrey and O. Diessel. A constructive proof of the Turing completeness of Circal. Technical report TR0214, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, September 2002.

[61]       J. Detrey and O. Diessel. SCCircal:  A static compiler mapping XCircal to Virtex FPGAs. Technical report TR0213, School of Computer Science and Engineering, University of New South Wales, UNSW Sydney, NSW, August 2002.

[62]       O. Diessel and G. Milne. HCircal:  A hardware compiler for Circal. Technical report ACRC–00–013, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Mawson Lakes, SA, Mar.  2000.

[63]       O. Diessel and G. Wigley. Opportunities for operating systems research in reconfigurable computing. Technical report ACRC–99–018, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Mawson Lakes, SA, Oct.  1999.

[64]       O. Diessel. On Scheduling Dynamic FPGA Reconfigurations — A Partial Rearrangement Approach. Ph.D. thesis, Department of Computer Science and Software Engineering, The University of Newcastle, Callaghan, Australia, Jan.  1998.

[65]       O. Diessel and H. ElGindy. Partial FPGA rearrangement by local repacking. Technical report 97–08, Department of Computer Science and Software Engineering, The University of Newcastle, Sept.  1997.

[66]       O. Diessel and H. ElGindy. Ordered partial task compaction on mesh connected computers. Technical report 96–11, Department of Computer Science and Software Engineering, The University of Newcastle, Sept.  1996.

[67]       O. Diessel. An investigation into the performance of a genetic algorithm for the selection of neural networks. B.E. project report, Department of Electrical Engineering and Computer Science, The University of Newcastle, Nov.  1990.

 

 

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